Memory with fail indicators, including memory with led fail indicators, and associated systems, devices, and methods
Memory with fail indicators, and associated systems, devices, and methods are disclosed herein. In one embodiment, a system includes a plurality of memory systems and a host device. At least one of the memory systems includes a fail indicator connected to the host device via a side channel of the system. The host device is configured to detect an occurrence of a failure on the at least one memory system and to initiate activation of the fail indicator. The side channel can be an I2C or I3C® side channel. The fail indicator, when activated, can provide a visual indication of the failure. For example, the fail indicator can include an LED that can be activated to emit light and provide an indication of the failure. A color of the light can correspond to a type, occurrence, or location of the failure on the at least one memory system.
1 . A system, comprising:
a plurality of dual in-line memory modules (DIMMs), each DIMM of the plurality including—
a registered clock driver (RCD),
a plurality of memory devices configured to communicate error information to the RCD via corresponding busses,
a fail indicator including a visual indicator,
a serial presence detect (SPD) hub, and
a local sideband bus coupling (a) the SPD hub to the RCD and (b) the SPD hub to the fail indicator independently of the RCD, wherein the RCD is configured to communicate the error information to the SPD hub via the local sideband bus; and
a host device connected to the SPD hub via a side channel of the system, wherein the host device is configured to:
receive, via the side channel, information from the SPD hub of a DIMM of the plurality of DIMMS,
based at least in part on the information, detect an occurrence of a failure on the DIMM, and
initiate activation of the visual indication of the fail indicator on the DIMM based at least in part on detection of the failure.
2 . The system of claim 1 , wherein the side channel includes an I3C® side channel.
3 . The system of claim 1 , wherein the fail indicator on each DIMM of the plurality of DIMMs is connected to the host device via the side channel, the respective SPD hub, and the respective local sideband bus.
4 . The system of claim 1 , wherein the visual indicator of each DIMM of the plurality of DIMMs includes a light emitting diode (LED), and wherein activation of the fail indicator on the DIMM includes activating the LED to emit light.
5 . The system of claim 4 , wherein a color of the light corresponds to a type, occurrence, or location of the failure on a DIMM of the plurality.
6 . The system of claim 1 , wherein the fail indicator on each DIMM of the plurality of DIMMs is dedicated to communicating failures corresponding to only that DIMM.
7 . The system of claim 1 , wherein the side channel includes an I2C side channel.
8 . The system of claim 1 , wherein the fail indicator of each DIMM of the plurality of DIMMs is directly coupled to the host device.
9 . A method, comprising:
receiving, via a side channel of a system, information from a serial presence detect (SPD) hub of a memory system, wherein the system includes a plurality of memory systems including the memory system, wherein each memory system of the plurality of memory systems includes (i) a respective registered clock driver and (ii) a respective SPD hub that is connected to a host device via the side channel, wherein each memory system of the plurality of memory systems further includes a fail indicator that has a visual indicator and that is coupled to the respective SPD hub via a respective local sideband bus and independently of the respective registered clock driver, and wherein each fail indicator is coupled to the host device via the respective sideband bus, the respective SPD hub, and the side channel;
detecting, based at least in part on the information, that a failure has occurred on the memory system; and
initiating activation of the visual indicator of the fail indicator of the memory system based at least in part on the detection of the failure, wherein initiating the activation of the visual indicator includes causing the visual indicator to provide an indication of an occurrence of the failure on the memory system.
10 . The method of claim 9 , wherein receiving the information via the side channel includes receiving the information via an I3C® side channel.
11 . The method of claim 9 , wherein:
the visual indicator of each fail indicator includes a light emitting diode (LED) or another light source; and
activation of the visual indicator of the fail indicator of the memory system includes switching the LED or other light source from a first state to a second state.
12 . The method of claim 11 , wherein the second state includes the LED or other light source emitting a color corresponding to a type or location of the failure.
13 . The method of claim 11 , further comprising selectively enabling or selectively disabling functionality of the visual indicator via an option in a basic input/output system (BIOS) connected to the memory system.
14 . The method of claim 9 , wherein receiving the information via the side channel includes receiving the information via an I2C side channel.
15 . The method of claim 9 , further comprising writing SPD information related to the failure in SPD bytes of the SPD hub of the memory system.
16 . The method of claim 9 , wherein the fail indicator of the memory system includes a plurality of visual indicators including the visual indicator, wherein each visual indicator of the plurality of visual indicators is dedicated to a different location on the memory system, and wherein initiating activation of the visual indicator includes switching a specific one of the plurality of visual indicators from a first state to a second state, and the specific one of the plurality of visual indicators corresponds to a location of the failure on the memory system.
17 . A memory system, comprising:
a plurality of memory devices, each configured to connect to a first host device via a data channel;
a serial presence detect (SPD) hub connected to a second host device via a side channel different from the data channel, and configured to provide an indication of detection of a failure on the memory system; and
a fail indicator coupled to the second host device (i) via the SPD hub and the side channel and (ii) separate from a registered clock driver, wherein the fail indicator is configured to, based at least in part on the indication of the detection of the failure, provide a visual indication of an occurrence of the failure on the memory system.
18 . The memory system of claim 17 , wherein the side channel includes an I3C® channel.
19 . The memory system of claim 17 , wherein:
the memory system includes a plurality of fail indicators including the fail indicator; and
each fail indicator of the plurality of fail indicators (a) is dedicated to a different subchannel of the data channel or to a different memory device of the plurality of memory devices and (b) is configured to provide a visual indication of an occurrence of a failure detected on a corresponding subchannel or a corresponding memory device of the plurality of memory devices.
20 . The memory system of claim 17 , wherein the memory system is a dual in-line memory module (DIMM), the plurality of memory devices includes a plurality of dynamic random-access memory (DRAM) devices, wherein the memory system further includes the registered clock driver, and wherein the registered clock driver is (a) connected to each memory device of the plurality of memory devices and (b) connected to the SPD hub via a local sideband bus.