Apparatus and method for performing debug control in chip
An apparatus and a method for performing debug control in a chip are provided, wherein the apparatus includes a first counter, a first determination circuit, a second counter and a second determination circuit. The first counter counts a number of execution times of a specific system request in the chip to generate a first counting result, and the first determination circuit generates a first determination result according to the first counting result. The second counter counts a number of cycles of an execution clock to generate a second counting result, and the second determination circuit generates a second determination result according to the second counting result. When the first determination result indicates that the first counting result reaches a first threshold and the second determination result indicates that the second counting result reaches a second threshold, execution of the chip is suspended at a breakpoint state.
1 . An apparatus for performing debug control in a chip, comprising:
a first counter, configured to count a number of execution times of a specific system request in the chip to generate a first counting result;
a first determination circuit, coupled to the first counter, configured to determine whether the first counting result reaches a first threshold to generate a first determination result;
a second counter, coupled to the first determination circuit, configured to count a number of cycles of an execution clock to generate a second counting result; and
a second determination circuit, coupled to the second counter, configured to determine whether the second counting result reaches a second threshold to generate a second determination result;
wherein when the first determination result indicates that the first counting result reaches the first threshold and the second determination result indicates that the second counting result reaches the second threshold, execution of the chip is suspended at a breakpoint state.
2 . The apparatus of claim 1 , further comprising:
a signal receiving circuit, configured to receive multiple system signals respectively corresponding to multiple system requests from multiple functional units in the chip; and
a signal selection circuit, coupled to the signal receiving circuit, configured to select a specific signal from the multiple system signals, wherein the specific signal corresponds to the specific system request.
3 . The apparatus of claim 2 , wherein when the apparatus receives an error message, the first counter is configured to count a number of times of receiving the specific signal according to the error message, in order to count the number of execution times of the specific system request.
4 . The apparatus of claim 1 , wherein when the first determination result indicates that the first counting result reaches the first threshold, the second counter starts counting the number of cycles of the execution clock to generate the second counting result.
5 . The apparatus of claim 1 , wherein the first threshold is determined according to a previous first counting result generated by the first counter at which the apparatus receives an error message during a previous execution of the chip, and the second threshold is determined according to a previous second counting result generated by the second counter at which the apparatus receives the error message during the previous execution of the chip, in order to set a state of the previous execution of the chip at which the apparatus receives the error message to be the breakpoint state.
6 . The apparatus of claim 1 , wherein the first threshold is determined according to a previous first counting result generated by the first counter at which the apparatus receives an error message during a previous execution of the chip, and the second threshold is sequentially set to be multiple candidate thresholds to make the execution of the chip be sequentially suspended at multiple candidate breakpoint states, wherein one of the multiple candidate thresholds is selected to be the second threshold according to the multiple candidate breakpoint states, to make the breakpoint state correspond to the error message received by the apparatus during the previous execution of the chip.
7 . The apparatus of claim 1 , wherein when the first determination result indicates that the first counting result reaches the first threshold and the second determination result indicates that the second counting result reaches the second threshold, a scan chain which connects multiple flip-flops in series is triggered to output values of the multiple flip-flops at the breakpoint state.
8 . The apparatus of claim 1 , wherein when the first determination result indicates that the first counting result reaches the first threshold and the second determination result indicates that the second counting result reaches the second threshold, a memory interface coupled to a memory device is triggered to capture data stored in the memory device at the breakpoint state.
9 . The apparatus of claim 1 , wherein when the first determination result indicates that the first counting result reaches the first threshold and the second determination result indicates that the second counting result reaches the second threshold, an in-circuit debugger is triggered to capture information of the apparatus at the breakpoint state.
10 . A method for performing debug control in a chip, comprising:
utilizing a first counter to count a number of execution times of a specific system request in the chip to generate a first counting result;
utilizing a first determination circuit to determine whether the first counting result reaches a first threshold to generate a first determination result;
utilizing a second counter to count a number of cycles of an execution clock to generate a second counting result;
utilizing a second determination circuit to determine whether the second counting result reaches a second threshold to generate a second determination result; and
in response to the first determination result indicating that the first counting result reaches the first threshold and the second determination result indicating that the second counting result reaches the second threshold, suspending execution of the chip at a breakpoint state.
11 . The method of claim 10 , further comprising:
utilizing a signal receiving circuit to receive multiple system signals respectively corresponding to multiple system requests from multiple functional units in the chip; and
utilizing a signal selection circuit to select a specific signal from the multiple system signals;
wherein the specific signal corresponds to the specific system request.
12 . The method of claim 11 , wherein utilizing the first counter to count the number of execution times of the specific system request in the chip to generate the first counting result comprises:
in response to the apparatus receiving an error message, utilizing the first counter to count a number of times of receiving the specific signal according to the error message, in order to count the number of execution times of the specific system request.
13 . The method of claim 10 , wherein utilizing the second counter to count the number of cycles of the execution clock to generate the second counting result comprises:
in response to the first determination result indicating that the first counting result reaches the first threshold, utilizing the second counter to start counting the number of cycles of the execution clock to generate the second counting result.
14 . The method of claim 10 , wherein the first threshold is determined according to a previous first counting result generated by the first counter at which the apparatus receives an error message during a previous execution of the chip, and the second threshold is determined according to a previous second counting result generated by the second counter at which the apparatus receives the error message during the previous execution of the chip, in order to set a state of the previous execution of the chip at which the apparatus receives the error message to be the breakpoint state.
15 . The method of claim 10 , wherein the first threshold is determined according to a previous first counting result generated by the first counter at which the apparatus receives an error message during a previous execution of the chip, and the second threshold is sequentially set to be multiple candidate thresholds to make the execution of the chip be sequentially suspended at multiple candidate breakpoint states, wherein one of the multiple candidate thresholds is selected to be the second threshold according to the multiple candidate breakpoint states, to make the breakpoint state correspond to the error message received by the apparatus during the previous execution of the chip.
16 . The method of claim 10 , further comprising:
in response to the first determination result indicating that the first counting result reaches the first threshold and the second determination result indicating that the second counting result reaches the second threshold, triggering a scan chain which connects multiple flip-flops in series to output values of the multiple flip-flops at the breakpoint state.
17 . The method of claim 10 , further comprising:
in response to the first determination result indicating that the first counting result reaches the first threshold and the second determination result indicating that the second counting result reaches the second threshold, triggering a memory interface coupled to a memory device to capture data stored in the memory device at the breakpoint state.
18 . The method of claim 10 , further comprising:
in response to the first determination result indicates that the first counting result reaches the first threshold and the second determination result indicates that the second counting result reaches the second threshold, triggering an in-circuit debugger to capture information of the apparatus at the breakpoint state.