Driving method for display panel, display driving device, and display device
A driving method for a display panel, display driving device, and display device are provided. The method includes: in a first clock cycle, displaying to-be-displayed data for (N−M)-th pixel row and obtaining to-be-displayed data for N-th pixel row expected to be displayed after a preset delay period from a start time of the first clock cycle, the preset delay period lasting for M clock cycles; and providing gate driving signals for (N−M+1)-th to (N 1 −1)-th pixel rows and inhibiting providing gate driving signals for N 1 -th to N 2 -th pixel rows in response to an error event in the to-be-displayed data for N-th pixel row, wherein a gate driving signal for each pixel row includes a pre-charging period and a displaying period, the pre-charging period lasts for Q clock cycles, and wherein N−M+Q+1≤N 1 ≤N, and N≤N 2 ≤T (a number of the plurality of pixel rows).
1 . A method for driving a display panel comprising a plurality of pixel rows, the method comprising:
displaying to-be-displayed data for (N−M)-th pixel row and obtaining to-be-displayed data for N-th pixel row in a first clock cycle, the to-be-displayed data for N-th pixel row being expected to be displayed after a preset delay period from a start time of the first clock cycle, and the preset delay period lasting for M clock cycles; and
providing gate driving signals for (N−M+1)-th to (N 1 −1)-th pixel rows and inhibiting providing gate driving signals for N 1 -th to N 2 -th pixel rows, in response to an error event in the to-be-displayed data for N-th pixel row, wherein a gate driving signal for each pixel row includes a pre-charging period and a displaying period, the pre-charging period lasts for Q clock cycles, and Q is less than M, and
wherein N 1 is greater than or equal to N−M+Q+1 and less than or equal to N, and N 2 is greater than or equal to N and less than or equal to a number of the plurality of pixel rows.
2 . The method of claim 1 , wherein N 1 is equal to N, and N 2 is equal to the number of the plurality of pixel rows,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, in response to the error event, the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows continue to be provided during the first clock cycle, and after the first clock cycle, the gate driving signals for (N−M+Q+1)-th to (N−1)-th pixel rows are provided, and the gate driving signals for N-th pixel row and all subsequent pixel rows are inhibited from being provided.
3 . The method of claim 1 , wherein N 1 is equal to N−M+Q+1, and N 2 is equal to the number of the plurality of pixel rows,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, in response to the error event, the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows continue to be provided during the first clock cycle, and after the first clock cycle, the gate driving signals for (N−M+Q+1)-th pixel row and all subsequent pixel rows are inhibited from being provided.
4 . The method of claim 1 , wherein N 1 is equal to N−p 1 , and N 2 is equal to N+p 2 ,
wherein, p 1 and p 2 are preset values; or
wherein p 1 is a preset value, and a value of p 2 depends on when the error event is eliminated or on a number of subsequent pixel rows after the N-th pixel row on the display panel.
5 . The method of claim 4 , wherein p 1 =1, and p 2 is the number of subsequent pixel rows after the N-th pixel row,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, in response to the error event, the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows continue to be provided during the first clock cycle, and after the first clock cycle, the gate driving signals for (N−M+Q+1)-th to (N−2)-th pixel rows are provided and the gate driving signals for (N−1)-th and all subsequent pixel rows are inhibited from being provided.
6 . The method of claim 1 , wherein a value of N 2 depends on when the error event is eliminated or on a number of subsequent pixel rows after the N-th pixel row on the display panel.
7 . The method of claim 1 , wherein the gate driving signal for each pixel row on the display panel is shifted based on a clock cycle, and
wherein a start time of the displaying period for N-th pixel row is a time after M clock cycles from the start time of the first clock cycle.
8 . The method of claim 1 , wherein the N-th pixel row performs display based on to-be-displayed data for N-th pixel row of a previous display frame when not being provided with a corresponding gate driving signal.
9 . The method of claim 1 , wherein the error event is caused by interference events including an electrostatic discharge (ESD) event.
10 . The method of claim 1 , further comprising:
latching the to-be-displayed data for N-th pixel row and allowing a corresponding gate driving signal for N-th pixel row to be provided, in response to an absence of the error event in the to-be-displayed data; and
releasing the latched to-be-displayed data in response to a release enable signal, so that the to-be-displayed data is enabled to be displayed in a respective displaying period in response to the corresponding gate driving signal.
11 . The method of claim 1 , wherein displaying to-be-displayed data for (N−M)-th pixel row comprises:
converting the to-be-displayed data for (N−M)-th pixel row into analog data signals and providing the same to the (N−M)-th pixel row, such that pixels on the (N−M)-th pixel row perform display according to the analog data signals.
12 . A display driving device for driving a display panel comprising a plurality of pixel rows, comprising:
a signal processing circuit configured to display to-be-displayed data for (N−M)-th pixel row and obtain to-be-displayed data for N-th pixel row in a first clock cycle, the to-be-displayed data for N-th pixel row being expected to be displayed after a preset delay period from a start time of the first clock cycle, and the preset delay period lasting for M clock cycles; and
an error detection circuit configured to detect an error event for each obtained to-be-displayed data when activated;
wherein the signal processing circuit is further configured to provide, in response to the error event in the to-be-displayed data for the (N-th) pixel row, gate driving signals for (N−M+1)-th to (N 1 −1)-th pixel rows and inhibit providing gate driving signals for N 1 -th to N 2 -th pixel rows, wherein a gate driving signal for each pixel row includes a pre-charging period and a displaying period, and the pre-charging period lasts for Q clock cycles, and Q is less than M, and
wherein N 1 is greater than or equal to N−M+Q+1 and less than or equal to N, and N 2 is greater than or equal to N and less than or equal to a number of the plurality of pixel rows.
13 . The display driving device according to claim 12 , wherein N 1 is equal to N, and N 2 is equal to the number of the plurality of pixel rows,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, the signal processing circuit is configured to: in response to the error event, continue to provide the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows during the first clock cycle, and after the first clock cycle, provide gate driving signals for (N−M+Q+1)-th to (N−1)-th pixel rows and inhibit provision of the gate driving signals for N-th pixel row and all subsequent pixel rows.
14 . The display driving apparatus according to claim 12 , wherein N 1 is equal to N−M+Q+1, and N 2 is equal to the number of the plurality of pixel rows,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, the signal processing circuit is configured to: in response to the error event, continue to provide the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows during the first clock cycle, and after the first clock cycle, inhibit provision of the gate driving signals for (N−M+Q+1)-th pixel row and all subsequent pixel rows.
15 . The display driving device of claim 12 , wherein N 1 is equal to N−p 1 , and N 2 is equal to N+p 2 ,
wherein, p 1 and p 2 are preset values; or
wherein p 1 is a preset value, and a value of p 2 depends on when the error event is eliminated or on a number of subsequent pixel rows after the N-th pixel row on the display panel.
16 . The display driving device of claim 15 , wherein p 1 =1, and p 2 is the number of the plurality of pixel rows minus N,
wherein, in the first clock cycle, driving periods corresponding to the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows have not ended, and
wherein, the signal processing circuit is configured to: in response to the error event, continue to provide the gate driving signals for (N−M)-th to (N−M+Q)-th pixel rows during the first clock cycle, and after the first clock cycle, provide the gate driving signals for (N−M+Q+1)-th to (N−2)-th pixel rows and inhibit provision of the gate driving signals for (N−1)-th and all subsequent pixel rows.
17 . The display driving device of claim 12 , wherein a value of N 2 depends on when the error event is eliminated or on a number of subsequent pixel rows after the N-th pixel row on the display panel.
18 . A display device comprising:
a display panel; and
a display driving device according to claim 12 , for driving the display panel.