Memory system and non-volatile memory with compressed soft bit data for error correction
According to an embodiment, a memory system includes a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller configured to control the non-volatile memory. The non-volatile memory is configured to output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller. The memory controller is configured to execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.
1 . A memory system comprising:
a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit; and
a memory controller configured to control the non-volatile memory,
wherein
the non-volatile memory is configured to output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller,
the memory controller is configured to execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data, and
a data size of the first hard bit data, a data size of the second hard bit data, a data size of the third hard bit data, and a data size of the fourth soft bit data are equal in size.
2 . The memory system according to claim 1 , wherein
the non-volatile memory is configured to calculate the fourth soft bit data based on a logical sum calculation using first soft bit data for the first bit, second soft bit data for the second bit, and third soft bit data for the third bit.
3 . The memory system according to claim 2 , wherein
the memory controller is configured to:
restore the first soft bit data based on the first hard bit data and the fourth soft bit data;
restore the second soft bit data based on the second hard bit data and the fourth soft bit data; and
restore the third soft bit data based on the third hard bit data and the fourth soft bit data.
4 . The memory system according to claim 2 , wherein
the first bit is determined by at least a first read operation based on a first state,
the first read operation includes a second read operation which uses a first voltage corresponding to the first state and a third read operation which uses a second voltage corresponding to the first state and higher than the first voltage,
the first hard bit data is determined based on at least the second read operation, and
the first soft bit data is obtained based on a calculation, the calculation using the first hard bit data and a result of the third read operation.
5 . The memory system according to claim 2 , wherein
the memory controller is configured to execute the error correction processing based on the first hard bit data, the second hard bit data, the third hard bit data, the first soft bit data, the second soft bit data, and the third soft bit data.
6 . A memory system comprising:
a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit; and
a memory controller configured to control the non-volatile memory,
wherein
the non-volatile memory is configured to
calculate the fourth soft bit data based on a logical sum calculation using first soft bit data for the first bit, second soft bit data for the second bit, and third soft bit data for the third bit, and
output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller,
the non-volatile memory further includes a counter configured to count a number of pieces of first logic level data of any of the first soft bit data, the second soft bit data, the third soft bit data, or the fourth soft bit data, and
the memory controller is configured to
read the number, and read the fourth soft bit data from the non-volatile memory if the number is equal to or larger than a preset determination value, and
execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.
7 . A non-volatile memory comprising:
a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit;
a word line commonly coupled to the memory cells;
a plurality of bit lines coupled to the memory cells, respectively; and
a sense amplifier coupled to the bit lines,
wherein the sense amplifier is configured to generate first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit, and
a data size of the first hard bit data, a data size of the second hard bit data, a data size of the third hard bit data, and a data size of the fourth soft bit data are equal in size.
8 . The non-volatile memory according to claim 7 , wherein
the fourth soft bit data is calculated based on a logical sum calculation using first soft bit data for the first bit, second soft bit data for the second bit, and third soft bit data for the third bit.
9 . The non-volatile memory according to claim 8 , wherein
the first bit is determined by at least a first read operation based on a first state,
the first read operation includes a second read operation which uses a first voltage corresponding to the first state and a third read operation which uses a second voltage corresponding to the first state and higher than the first voltage,
the first hard bit data is determined based on at least the second read operation, and
the first soft bit data is obtained based on a calculation, the calculation using the first hard bit data and a result of the third read operation.
10 . The non-volatile memory according to claim 8 , further comprising:
a counter configured to count a number of pieces of first logic level data of any of the first soft bit data, the second soft bit data, the third soft bit data, or the fourth soft bit data.