Power supply generator assist
The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
1 . A voltage assist circuit configured to selectively supply an assist voltage signal to a power supply generator in response to a load, the voltage assist circuit comprising:
a charge pump;
a driver circuit receiving a control signal from the charge pump;
a first control circuit configured to control the voltage assist circuit in response to the control signal from the charge pump, wherein the first control circuit includes:
a replica driver circuit that matches the driver circuit and is configured to mimic operations of the driver circuit in order to accurately determine a bias gate voltage needed to disable the driver circuit;
a second control circuit configured to control the voltage assist circuit in response to the assist voltage signal supplied by the driver circuit in response to demands of the load; and
a control logic circuit, wherein the control logic circuit is connected to an output of the first control circuit and an output of the second control circuit.
2 . The voltage assist circuit of claim 1 , wherein, upon detecting that a supply of the assist voltage signal is needed to assist the power supply generator in response to the load, the second control circuit is configured to enable the driver circuit to inject a drive current.
3 . The voltage assist circuit of claim 1 , wherein the load includes one or more memory cells.
4 . The voltage assist circuit of claim 3 , wherein the one or more memory cells are Magnetoresistive Random Access Memory (MRAM) cells.
5 . The voltage assist circuit of claim 3 , wherein the assist voltage signal is connected to a bit line voltage of the one or more memory cells.
6 . The voltage assist circuit of claim 1 , wherein the driver circuit includes one or more distributed NMOS driver circuits.
7 . The voltage assist circuit of claim 6 , wherein each of the one or more distributed NMOS driver circuits comprises an NMOS transistor and a PMOS transistor, wherein:
a drain terminal of the NMOS transistor is connected to a power supply;
a gate terminal of the NMOS transistor is connected to the control signal;
a source terminal of the NMOS transistor is connected to a source terminal of PMOS transistor;
a gate terminal of the PMOS transistor is connected to a bias voltage; and
a drain terminal of the PMOS transistor is connected to the power supply generator.
8 . The voltage assist circuit of claim 7 , wherein the enabling the one or more distributed NMOS driver circuits includes boosting the gate voltage of the NMOS transistor to be greater than or equal to a target level, wherein the target level is a sum of the assist voltage signal and a threshold voltage of the NMOS transistor.
9 . The voltage assist circuit of claim 7 , wherein disabling the one or more distributed NMOS driver circuits includes regulating a gate voltage of the NMOS transistor to be less than the target level, wherein the target level is a sum of the assist voltage signal and a threshold voltage of the NMOS transistor.
10 . The voltage assist circuit of claim 1 , wherein the second control circuit includes a voltage divider circuit connected to the assist voltage signal and a comparator circuit connected to an output of the voltage divider circuit and configured to compare a fraction of the assist voltage signal to a reference voltage to determine whether the driver circuit should be enabled.
11 . The voltage assist circuit of claim 1 , wherein the replica driver circuit of the first control circuit includes an NMOS transistor and a PMOS transistor, wherein a drain terminal of the NMOS transistor of the replica driver circuit and a gate terminal of the NMOS transistor of the replica driver circuit are tied to an output of the charge pump, a source terminal of the NMOS transistor of the replica driver circuit is connected to a source terminal of the PMOS transistor and a gate terminal of the PMOS transistor of the replica driver circuit is tied to ground.
12 . The voltage assist circuit of claim 11 , wherein the first control circuit further includes
a voltage divider circuit connected to a drain terminal of the PMOS transistor of the replica driver circuit; and
a comparator circuit connected to the output of the voltage divider circuit and configured to compare a fraction of the bias gate voltage of the driver circuit to a reference voltage to determine whether the driver circuit should be disabled.
13 . The voltage assist circuit of claim 1 , further comprising a switch to control an operation of the voltage assist circuit, wherein the voltage assist circuit is turned on by turning on the switch and turned off by turning off the switch.
14 . A method of selectively providing a voltage assist signal to a power supply generator in response to a load, the method comprising:
outputting a control signal to an assist driver circuit from a charge pump;
outputting a first enable signal to the charge pump in response to a first voltage assist signal level being less than a reference voltage, to regulate the control signal at a first level to turn on the assist driver circuit and inject a current to the load; and
outputting a second enable signal to the charge pump in response to a second control signal level being less than the reference voltage, to regulate the control signal at a second level to maintain the control signal at a predetermined voltage level, wherein maintaining the control signal at the predetermined voltage level includes:
detecting a voltage level of the control signal;
upon determining that the voltage level of the control signal is higher than the predetermined voltage level, turning the assist driver circuit on; and
upon determining that the voltage level of the control signal is lower than the predetermined voltage level, turning the assist driver circuit off.
15 . The method of claim 14 , wherein the assist driver circuit includes one or more distributed NMOS driver circuits, wherein each of the one or more distributed NMOS driver circuits comprises an NMOS transistor and a PMOS transistor, wherein:
a drain terminal of the NMOS transistor is connected to a power supply;
a gate terminal of the NMOS transistor is connected to an output of a charge pump circuit;
a source terminal of the NMOS transistor is connected to a source terminal of PMOS transistor;
a gate terminal of the PMOS transistor is connected to a bias voltage; and
a drain terminal of the PMOS transistor is connected to the output of the power supply generator circuit.
16 . The method of claim 15 , wherein the turning the assist driver circuit on includes boosting a gate voltage level at the gate terminal of the NMOS transistor to be greater than or equal to a target level, wherein the target level is a sum of the voltage assist signal and a threshold voltage of the NMOS transistor.
17 . The method of claim 15 , wherein turning the assist driver circuit off includes regulating a gate voltage level at the gate terminal of the NMOS transistor to be less than a target level, wherein the target level is a sum of the voltage assist signal and a threshold voltage of the NMOS transistor.
18 . A voltage assist circuit to selectively supply an assist voltage to a power supply generator in order to meet power demands of a memory cell, the voltage assist circuit comprising:
a driver circuit configured to inject a drive current to an output of the voltage assist circuit when enabled;
a charge pump circuit connected to an input of the driver circuit and configured to control an operation of the driver circuit;
an active level detector circuit connected to an output of the driver circuit and configured to detect a bit line voltage of the memory cell;
a standby level detector circuit connected to the input of the driver circuit, wherein the standby level detector circuit includes a replica driver circuit that matches the driver circuit and is configured to mimic operations of the driver circuit; and
a control logic circuit, wherein outputs of the active level detector circuit and the standby level detector circuit are connected to inputs of the control logic circuit and an output of the control logic circuit is connected to an input of the charge pump circuit.
19 . The voltage assist circuit of claim 18 , wherein, upon detecting that the memory cell is performing a write operation and in need of a current injection, the active level detector circuit is configured to produce a first output enable signal that controls an operation of the charge pump circuit in order to boost an output of the charge pump circuit to a target level.
20 . The voltage assist circuit of claim 18 , wherein, upon detecting that the memory cell is in a standby mode, the standby level detector circuit is configured to produce a second output enable signal that regulates an operation of the charge pump circuit such that the output of the charge pump circuit remains at a target level during the standby mode.