SRAM memory with random deterministic initialization
View Patent ↗Static random access memory device comprising a matrix in which each column is associated with an initialization circuit ( 100 i, 100 j ), provided with a stage ( 110 ) for drawing a random value ( 110 ), configured to, following the reception of the initialization activation signal (RAND_ENABLE), produce, in a random manner, respectively a first potential at a first node (NA) corresponding to a given logic state and a second potential at a second output node (NB) different from the first potential and corresponding to a given logic state complementary to said given logic state, in order to initialize cells of a same column to a given state selected randomly between two states.
1 . A memory device comprising a memory matrix arranged in rows and columns of SRAM memory cells, each column comprising a first bit line and a second complementary bit line respectively connected to access transistors of the memory cells of the column, each column being associated with an initialization circuit comprising a first coupling element and a second coupling element positioned respectively between, on the one hand, the first and second bit lines of the associated column and, on the other hand, a control unit, the control unit being configured to impose a voltage on the bit lines when at least one of said coupling elements is rendered conductive in a deterministic initialization mode of all or some of the cells of the column, and wherein said control unit comprises at least a random value drawing stage for drawing a random value, said random value corresponding to a logical value, or a logic state from two possible values or logic states ‘0’ or ‘1’, and wherein, in a random deterministic initialization phase, the control unit is configured to successively control for a selected column to:
generate by said random value drawing stage a random value associated with said selected column; then
activate of a coupling element among said first and second coupling elements of the initialization circuit associated with said selected column in order to connect at least one of the bit lines to the control unit which imposes a voltage value, the activated coupling element among said first and second coupling elements or the voltage value imposed by the control unit, being dependent of said generated random value for said selected column, and
simultaneously activate access transistors of at least one cell of said selected column,
wherein the random value drawing stage is able to be coupled to a column of cells from said columns and provided with a first output node and a second output node, said random value drawing stage being configured to, following the reception of an initialization activation signal, produce, in a random manner, respectively a first potential at the first node corresponding to a given logic state and a second potential at the second output node different from the first potential and corresponding to a given logic state complementary to said given logic state, and
wherein at least one first initialization circuit associated with a first column being configured to, prior to a random deterministic initialization phase:
isolate the first output node and the second output node respectively from a first bit line and a second bit line of said first column,
then, during the random deterministic initialization phase triggered by the reception of said initialization activation signal,
allow the first output node and the second node to be set respectively at different potentials, while coupling the first output node to said first bit line and the second output node to said second bit line of the first column.
2 . The memory device according to claim 1 , wherein
prior to the random deterministic initialization phase, the first output node and the second output node are isolated respectively from the first bit line and the second bit line of said first column while the first output node and the second node are set to a same potential.
3 . The memory device according to claim 1 , wherein said random value drawing stage is provided with a first inverter and a second inverter that are cross-coupled.
4 . The memory device according to claim 1 , wherein the initialization circuit comprises:
a transistor switching stage, arranged between a first biasing element and the output nodes of said random value drawing stage is configured to, outside random deterministic initialization phases, connect the output nodes of said random value drawing stage to the first biasing element and to isolate the output nodes of the random value drawing stage from said first biasing element during said random deterministic initialization phases,
a switch element, in particular a transistor, configured to, outside said random deterministic initialization phases, isolate said stage for drawing a random value from a second biasing element and during said random deterministic initialization phases, connect said random value drawing stage to said second biasing element.
5 . The memory device according to claim 4 , wherein the transistor switching stage is further configured, outside of said random deterministic initialization phases, to isolate the output nodes of said random value drawing stage from one another and, during said random deterministic initialization phases, to connect the output nodes of said random value drawing stage to one another.
6 . The memory device according to claim 1 , wherein the first coupling element is a first coupling transistor between the first bit line and a first output node of the random value drawing stage, wherein the second coupling element is a second coupling transistor arranged between the second bit line and a second output node of the random value drawing stage, the first coupling transistor and the second coupling transistor being controlled by said random deterministic initialization activation signal.
7 . The memory device according to claim 1 , wherein said random value drawing stage comprises a shared stage for drawing a random number over several bits, each bit being associated with a column.
8 . The memory device according to claim 1 , wherein a first column is provided with a first random value drawing stage, a second column being provided with a second random value drawing stage.
9 . The memory device according to claim 1 , wherein at least part of the memory cell matrix includes so-called sensitive cells and comprising a memory controller able to impose a random deterministic initialization of these sensitive cells when the memory device is powered up or following an operation to delete the memory matrix.