Phased array transmitter
A phase shifter including a quadrature generator configured to generate an in phase (I) signal and a quadrature (Q) signal from an input signal; an in phase vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal; and an auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I configured to receive the I signal, the auxiliary VM_Q configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q configured to receive a bias signal and configured to adjust an in phase amplitude output of the VM_I and a quadrature amplitude output of the VM_Q responsive to the bias signal.
1 . A phase shifter, comprising:
a quadrature generator configured to generate an in phase (I) signal and a quadrature (Q) signal from an input signal;
an in phase vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal; and
an auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I configured to receive the I signal, the auxiliary VM_Q configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q configured to receive a bias signal at respective inputs of the auxiliary VM_I and the auxiliary VM_Q and configured to adjust an in phase amplitude output of the VM_I and a quadrature amplitude output of the VM_Q responsive to the bias signal.
2 . The phase shifter of claim 1 , wherein the bias signal is a fixed bias signal.
3 . The phase shifter of claim 1 , wherein the bias signal is an adaptive bias signal responsive to a level of the input signal.
4 . The phase shifter of claim 1 , wherein the auxiliary VM_I and the auxiliary VM_Q comprise cascode devices configured to adjust a direction of a phase rotation of a combined output of the VM_I and the VM_Q.
5 . The phase shifter of claim 1 , wherein the auxiliary VM_I and the auxiliary VM_Q comprise a single bit architecture.
6 . The phase shifter of claim 1 , wherein the auxiliary VM_I and the auxiliary VM_Q comprise a multiple bit architecture.
7 . The phase shifter of claim 1 , wherein the phase shifter is arranged in a phased array including multiple phase shifters, and the VM_I and the VM_Q of each phase shifter are configured to provide a phase offset with respect to the signals provided by the VM_I and the VM_Q of other phase shifters, while the auxiliary VM_I and the auxiliary VM_Q of each phase shifter provide a common phase shift with respect to the signals provided by the auxiliary VM_I and the auxiliary VM_Q of the other phase shifters.
8 . The phase shifter of claim 3 , wherein the adaptive bias signal compensates for the amplitude modulation (AM) to phase modulation (PM) distortion of a power amplifier.
9 . The phase shifter of claim 3 , wherein the adaptive bias signal is generated by a bias circuit responsive to an input signal of the bias circuit being above a threshold voltage.
10 . The phase shifter of claim 1 , further comprising a vector modulator driver amplifier configured to receive the input signal.
11 . The phase shifter of claim 1 , further comprising a combining circuit configured to combine the adjusted output of the VM_I and the adjusted output of the VM_Q.
12 . A method for signal transmission, comprising:
generating an in phase (I) amplitude and a quadrature (Q) amplitude based on an input signal;
generating an auxiliary in phase amplitude and an auxiliary quadrature amplitude based on the input signal and a gain signal, the gain signal corresponding to the auxiliary in phase amplitude and the auxiliary quadrature amplitude; and
adjusting the in phase amplitude using the auxiliary in phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.
13 . The method of claim 12 , further comprising adjusting the in phase amplitude and adjusting the quadrature amplitude responsive to a bias signal.
14 . The method of claim 13 , wherein the bias signal is fixed.
15 . The method of claim 13 , wherein the bias signal is adaptive responsive to a level of a differential input signal.
16 . The method of claim 15 , further comprising adjusting the in phase amplitude and adjusting the quadrature amplitude to one of a lead or lag vector associated with the in phase amplitude and the quadrature amplitude.
17 . The method of claim 12 , further comprising generating the auxiliary in phase amplitude and the auxiliary quadrature amplitude using a single bit architecture.
18 . The method of claim 12 , further comprising generating the auxiliary in phase amplitude and the auxiliary quadrature amplitude using a multiple bit architecture.
19 . A device, comprising:
means for generating an in phase (I) amplitude and a quadrature (Q) amplitude based on an input signal;
means for generating an auxiliary in phase amplitude and an auxiliary quadrature amplitude based on the input signal and a gain signal, the gain signal corresponding to the auxiliary in phase amplitude and the auxiliary quadrature amplitude; and
means for adjusting the in phase amplitude using the auxiliary in phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.
20 . The device of claim 19 , further comprising means for adjusting the in phase amplitude and adjusting the quadrature amplitude responsive to a bias signal.