Granted Patent B2

US 12,647,186 · App. 18/425,628 · Granted Jun 2, 2026

Inventors: Michael Y. Frankel (Hallandale Beach, FL); Vladimir Pelekhaty (Baltimore, MD)

Assignee: Ciena Corporation

H04B10/616H04B10/071

Abstract

Claims (32)

1 . A circuit for use in an optical receiver, the circuit comprising:

an input configured to receive current from a photodetector;

an amplifier stage connected to the input; and

a feedback path connected to the amplifier stage and to an output, wherein the feedback path includes a feedback element and an operating mode switch configured to set one of photodetector amplifier with dynamic load (PADL) mode and an integrate-and-dump (I&D) mode,

wherein the feedback element comprises an active dynamic load transistor configured to terminate the current from the photodetector, and wherein the operating mode switch is coupled to a control terminal of the active dynamic load transistor and is configured to selectively couple the control terminal to the output in the PADL mode and to a clock signal in the I&D mode such that the active dynamic load transistor functions as a sampling gate in the I&D mode.

2 . The circuit of claim 1 , wherein the operating mode switch, in the PADL mode, connects the feedback element to the output, and, in the I&D mode, connects the feedback element to a clock signal which determines a sampling window.

3 . The circuit of claim 2 , wherein the clock signal is synchronized to incoming data on the input.

4 . The circuit of claim 1 , wherein the feedback element is a P-channel metal-oxide-semiconductor (PMOS) transistor.

5 . The circuit of claim 1 , wherein the feedback element is a N-channel metal-oxide-semiconductor (NMOS) transistor.

6 . The circuit of claim 1 , wherein the operating mode switch is a complementary metal-oxide-semiconductor (CMOS) transmission gate.

7 . The circuit of claim 1 , wherein the amplifier stage is a complementary metal-oxide-semiconductor (CMOS) inverter.

8 . The circuit of claim 1 , wherein the PADL mode is for higher baud operation than the I&D mode.

9 . The circuit of claim 1 , wherein the operating mode switch is set based on a data rate of the optical receiver wherein the operating mode switch is configured to set the PADL mode for a higher data rate and to set the I&D mode for a lower data rate.

10 . The circuit of claim 1 , wherein the optical receiver is in a satellite optical modem that is configured to operate over a wide range of data rate operation, such that the operating mode switch is set based on the data rate operation.

11 . The circuit of claim 1 , wherein the optical receiver is in a terrestrial free space optical link having variable channel impairments, such that the operating mode switch is set based on the variable channel impairments.

12 . The circuit of claim 1 , wherein the optical receiver is in an optical time domain reflectometer (OTDR) that operates over a range of optical sampling pulse widths, such that the operating mode switch is set based on the optical sampling pulse widths.

13 . An optical modem comprising:

an optical front end configured to provide a current to an adjustable bandwidth current-to-voltage converter, the adjustable bandwidth current-to-voltage converter includes

an amplifier stage configured to receive the voltage; and

a feedback path connected to the amplifier stage and to an output, wherein the feedback path includes a feedback element and an operating mode switch configured to set one of a photodetector amplifier with dynamic load (PADL) mode and an integrate-and-dump (I&D) mode wherein the feedback element comprises an active dynamic load transistor configured to terminate the current from the optical front end, and wherein the operating mode switch is coupled to a control terminal of the active dynamic load transistor and is configured to selectively couple the control terminal to the output in the PADL mode and to a clock signal in the I&D mode such that the active dynamic load transistor functions as a sampling gate in the I&D mode.

14 . The optical modem of claim 13 , wherein the PADL mode is for higher baud operation than the I&D mode.

15 . The optical modem of claim 13 , wherein the operating mode switch is set based on a data rate of the optical modem, wherein the operating mode switch is configured to set the PADL mode for a higher data rate and to set the I&D mode for a ower data rate.

16 . The optical modem of claim 13 , wherein the optical modem is in a satellite and is configured to operate over a wide range of data rate operation, such that the operating mode switch is set based on the data rate operation.

17 . The optical modem of claim 13 , wherein the optical modem is in a terrestrial free space optical link having variable channel impairments, such that the operating mode switch is set based on the variable channel impairments.

18 . The optical modem of claim 13 , wherein the optical modem is in an optical time domain reflectometer (OTDR) that operates over a range of optical sampling pulse widths, such that the operating mode switch is set based on the optical sampling pulse widths.

19 . A method comprising steps of:

receiving current from a photodetector associated with an optical receiver;

converting the current into voltage;

configuring a feedback path after the converting in one of photodetector amplifier with dynamic load (PADL) mode and an integrate-and-dump (I&D) mode, wherein the configuring is based on a baud rate of the optical receiver; and

providing an output that includes a voltage converted from current, the output being adjusted by the feedback path,

wherein the configuring comprises, in the PADL mode, coupling a control terminal of an active dynamic load transistor to the output such that an output voltage controls a conductance of the active dynamic load transistor to terminate the current from the photodetector, and, in the I&D mode, coupling the control terminal of the active dynamic load transistor to a clock signal such that the active dynamic load transistor functions as a sampling gate and a sampling window is determined by the clock signal.

20 . The method of claim 19 , wherein the PADL mode is for higher baud operation than the I&D mode.

Assignments (1)

Continuity (1)

References Cited (64)