Semiconductor structure and method for forming the same
View Patent ↗A semiconductor structure includes a substrate having a peripheral region and a memory region. A plurality of bit lines are disposed on the substrate, extending along a first direction to pass through the peripheral region and the memory region, and arranged in parallel along a second direction, wherein the first direction and the second direction are is perpendicular. A plurality of insulating plugs and first spacer structures are alternately arranged along the first direction between the bit lines on the peripheral region. A plurality of conductive plugs and second spacer structures are alternately arranged along the first direction between the bit lines on the memory region. The first spacer structures and the second spacer structures comprise a same material, and along the first direction, widths of the second spacer structures are smaller than widths of the first spacer structures.
1 . A semiconductor structure, comprising:
a substrate comprising a peripheral region and a memory region;
a plurality of bit lines disposed on the substrate, extending along a first direction to pass through the peripheral region and the memory region, and arranged in parallel along a second direction, wherein the first direction and the second direction are is perpendicular;
a plurality of insulating plugs and first spacer structures alternately arranged along the first direction between the bit lines on the peripheral region; and
a plurality of conductive plugs and second spacer structures alternately arranged along the first direction between the bit lines on the memory region, wherein the first spacer structures and the second spacer structures comprise a same material, and along the first direction, widths of the second spacer structures are smaller than widths of the first spacer structures.
2 . The semiconductor structure according to claim 1 , wherein edges of the first spacer structures that contact the insulating plugs respectively have a convex curved profile, and edges of the second spacer structures that contact the conductive plugs respectively have a concave curved profile.
3 . The semiconductor structure according to claim 1 , further comprising a plurality of third spacer structures disposed on a boundary region between the peripheral region and the memory region along the second direction, wherein along the first direction, width of the third spacer structures are smaller than the widths of the first spacer structures, and are larger than the widths of the second spacer structures.
4 . The semiconductor structure according to claim 3 , wherein each of the third spacer structures comprises an edge in contact with one of the insulating plugs and having a convex curved profile, and another edge in contact with one of the conductive plugs and having a concave curved profile.
5 . The semiconductor structure according to claim 1 , wherein top surfaces of the second spacer structures are lower than the top surfaces of the first spacer structures.
6 . The semiconductor structure according to claim 1 , further comprising a plurality of sidewall spacers disposed along sidewalls of the bit lines, wherein thicknesses of portions of the sidewall spacers between the conductive plugs and the bit lines are smaller than thicknesses of portions of the sidewall spacers between the insulating plugs and the bit lines.
7 . The semiconductor structure according to claim 6 , wherein the first spacer structures and the second spacer structures respectively extend through the sidewall spacers to directly contact the sidewalls of the bit lines.
8 . The semiconductor structure according to claim 6 , wherein edges of the first spacer structures in contact with the insulating plugs and edges of the first spacer structures in contact with the sidewall spacers are jointed at notch portions of the first spacer structures.
9 . The semiconductor structure according to claim 1 , wherein the first spacer structures and the second spacer structures respectively comprise an air gap.
10 . The semiconductor structure according to claim 1 , wherein the first spacer structures and the second spacer structures comprise silicon nitride, the insulating plugs comprise silicon oxide, the conductive plugs respectively comprise a lower portion comprising poly silicon and an upper portion comprising tungsten.
11 . The semiconductor structure according to claim 1 , further comprising:
a plurality of active regions disposed in the memory region of the substrate, respectively having a length extending along a third direction and being arranged into a staggered array, wherein the third direction is different from the first direction and the second direction; and
a plurality of word lines disposed in the substrate, extending along the second direction and parallel to each other along the first direction to divide each of the active regions into a middle portion and two terminal portions, wherein the second spacer structures are aligned along the second direction and located directly above the word lines, the middle portions of the active regions are respectively in electrical contact with the bit lines, and the terminal portions of the active regions are respectively in electrical contact with the conductive plugs.