Integrated circuit device and electronic system including the same
An integrated circuit device includes a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction. The channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer. The pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.
1 . An integrated circuit device comprising:
a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction;
a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction; and
a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction,
wherein the channel structure includes:
a core insulating layer;
a channel layer on a side wall and a bottom surface of the core insulating layer;
an information storage layer on an outside wall of the channel layer; and
a pad pattern covering a top surface of the core insulating layer,
wherein the pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.
2 . The integrated circuit device of claim 1 , wherein a first vertical length from a topmost surface of the pad pattern to the topmost surface of the information storage layer is greater than a second vertical length from the topmost surface of the pad pattern to a topmost surface of the channel layer.
3 . The integrated circuit device of claim 2 , wherein an outside wall of the pad pattern is coplanar with an outside wall of the information storage layer.
4 . The integrated circuit device of claim 1 , wherein a topmost surface of the channel layer has an angled shape with respect to the horizontal direction, and the core insulating layer is arranged along the topmost surface.
5 . The integrated circuit device of claim 1 , wherein the topmost surface of the information storage layer has an angled shape with respect to the horizontal direction, and the pad pattern is arranged along the topmost surface.
6 . The integrated circuit device of claim 1 , wherein a first horizontal width of a first portion of the core insulating layer is less than a second horizontal width of a second portion of the core insulating layer, wherein a side wall of the first portion of the core insulating layer contacts the channel layer, and a side wall of the second portion of the core insulating layer contacts the pad pattern.
7 . The integrated circuit device of claim 6 , wherein a topmost surface of the second portion of the core insulating layer has a curved shape, and the pad pattern is arranged along the curved shape of the second portion of the core insulating layer.
8 . The integrated circuit device of claim 1 , wherein:
an uppermost conductive line among the plurality of conductive lines corresponds to a string select line, and
a side wall of the string select line faces a side wall of the pad pattern.
9 . The integrated circuit device of claim 8 , wherein a vertical level of a bottom surface of the string select line is equal to a vertical level of a bottommost surface of the pad pattern.
10 . The integrated circuit device of claim 1 , wherein the information storage layer includes a ferroelectric material.
11 . An integrated circuit device comprising:
a semiconductor substrate including a cell region and a connection region adjacent to the cell region;
a gate stack extending in a first direction and a second direction, including a plurality of conductive lines and a plurality of insulating layers, and having a stepped structure in the connection region, the first and second directions being parallel to a top surface of the semiconductor substrate and crossing each other, the plurality of conductive lines and the plurality of insulating layers being alternately stacked in a third direction that is orthogonal to the top surface of the semiconductor substrate;
a channel structure in the cell region and extending through the gate stack in the third direction; and
a plurality of contact plugs in the connection region and respectively contacting respective end portions of the plurality of conductive lines,
wherein the channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, a ferroelectric layer on an outside wall of the channel layer, a dielectric layer on an outside wall of the ferroelectric layer, and a pad pattern covering a top surface of the core insulating layer,
wherein the pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the ferroelectric layer, and
wherein a side wall of an uppermost conductive line among the plurality of conductive lines faces a side wall of the pad pattern.
12 . The integrated circuit device of claim 11 , wherein:
the pad pattern includes: a side wall portion on the ferroelectric layer; and a central portion on the core insulating layer, and
a first thickness of the side wall portion in the third direction is greater than a second thickness of the central portion in the third direction.
13 . The integrated circuit device of claim 12 , wherein:
a top surface of the central portion of the pad pattern has a flat shape, and
a bottom surface of the central portion of the pad pattern has a curved shape that is convex downwards.
14 . The integrated circuit device of claim 12 , wherein:
an inside wall of the side wall portion of the pad pattern contacts a side wall of the core insulating layer and the outside wall of the channel layer, and
an outside wall of the side wall portion of the pad pattern contacts an inside wall of the dielectric layer.
15 . The integrated circuit device of claim 11 , wherein:
an outside wall of the pad pattern is coplanar with the outside wall of the ferroelectric layer, and
the outside wall of the pad pattern and the outside wall of the ferroelectric layer contact an inside wall of the dielectric layer.
16 . The integrated circuit device of claim 11 , wherein a first horizontal width of a first portion of the core insulating layer is less than a second horizontal width of a second portion of the core insulating layer, wherein a side wall of the first portion of the core insulating layer contacts the channel layer, and a side wall of the second portion of the core insulating layer contacts the pad pattern.
17 . The integrated circuit device of claim 16 , wherein:
a void extends lengthwise in the third direction in the first portion of the core insulating layer, and
the pad pattern is separated from the void by the second portion of the core insulating layer.
18 . The integrated circuit device of claim 11 , wherein a vertical level of a topmost surface of the channel layer is higher than a vertical level of the topmost surface of the ferroelectric layer.
19 . An electronic system comprising:
a main board;
an integrated circuit device on the main board; and
a controller on the main board and electrically connected to the integrated circuit device,
wherein the integrated circuit device includes:
a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction;
a plurality of insulating layers alternating in a vertical direction with the plurality of conductive lines and extending in the horizontal direction; and
a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction,
wherein the channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer, and
wherein the pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.
20 . The electronic system of claim 19 , wherein:
the main board includes wiring patterns electrically connecting the integrated circuit device to the controller, and
a first vertical length from a topmost surface of the pad pattern to the topmost surface of the information storage layer is greater than a second vertical length from the topmost surface of the pad pattern to a topmost surface of the channel layer.