Multi-layer image sensor structure with dark current sensing photodiodes in black level calibration area surrounded by dual seal ring system and opaque cover with integrated trench isolation
An image sensor includes a substrate having first and second surfaces opposite to each other, an image pixel area, and a black level calibration (BLC) area adjacent to the image pixel area. The BLC area includes a dark current sensing circuit including photo diodes disposed in the substrate, a first seal ring disposed over the second surface and surrounding the image pixel area in plan view, a second seal ring disposed over the second surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first and second seal rings, an opaque cover disposed over the first surface and covering the dark current sensing circuit, the first and second seal rings, and one or more first trench isolation structures extending from the first surface to an inside the substrate and disposed between the first seal ring and the opaque cover.
1 . A complementary metal-oxide-semiconductor (CMOS) image sensor, comprising:
a substrate having a first principal surface and a second principal surface opposite to the first principal surface;
an image pixel area including a plurality of photo diodes disposed in the substrate and a plurality of color filters disposed over the first principal surface of the substrate; and
a black level calibration area adjacent to the image pixel area for determining a dark voltage current,
wherein the black level calibration area comprises:
a dark current sensing circuit including one or more photo diodes disposed in the substrate;
a first seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view;
a second seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first seal ring structure and the second seal ring structure;
an opaque cover layer disposed over the first principal surface and covering the dark current sensing circuit, the first seal ring structure and the second seal ring structure; and
one or more first trench isolation structures extending from the first principal surface to an inside of the substrate and disposed between the first seal ring structure and the opaque cover layer in plan view.
2 . The CMOS image sensor of claim 1 , wherein the black level calibration area further comprises one or more second trench isolation structures extending from the second principal surface to the inside the substrate and disposed between the first seal ring structure and the opaque cover layer.
3 . The CMOS image sensor of claim 2 , wherein a depth of the one or more first trench isolation structures is greater than a depth of the one or more second trench isolation structures.
4 . The CMOS image sensor of claim 3 , wherein the black level calibration area further comprises one or more third trench isolation structures extending from the first principal surface to the inside the substrate and disposed between the second seal ring structure and the opaque cover layer.
5 . The CMOS image sensor of claim 4 , wherein the black level calibration area further comprises one or more fourth trench isolation structures extending from the second principal surface to the inside the substrate and disposed between the second seal ring structure and the opaque cover layer.
6 . The CMOS image sensor of claim 5 , wherein a depth of the one or more third trench isolation structures is greater than a depth of the one or more fourth trench isolation structures.
7 . The CMOS image sensor of claim 4 , wherein the black level calibration area further comprises one or more fifth trench isolation structures extending from the first principal surface to the inside the substrate and disposed between the dark current sensing circuit and the opaque cover layer.
8 . The CMOS image sensor of claim 1 , wherein a thickness of a first portion of the opaque cover layer overlapping the first seal ring structure and a thickness of a second portion of the opaque cover layer overlapping the second seal ring structure in plan view are smaller than a thickness of a third portion of the opaque cover layer overlapping the dark current sensing circuit.
9 . A complementary metal-oxide-semiconductor (CMOS) image sensor, comprising:
a first semiconductor circuit, including:
a first substrate having a first principal surface and a second principal surface opposite to the first principal surface;
an image pixel area including a plurality of photo diodes disposed in the first substrate and a plurality of color filters disposed over the first principal surface of the first substrate;
a black level calibration area adjacent to the image pixel area for determining a dark voltage current; and
a first wiring structure coupled to the plurality of photo diodes; and
a second semiconductor circuit, including:
a second substrate having a first principal surface and a second principal surface opposite to the first principal surface;
a plurality of transistors disposed over the first principal surface of the second substrate; and
a second wiring structure coupled to the plurality of transistors, wherein:
the first semiconductor circuit is attached to the second semiconductor circuit such that the second principal surface of the first substrate faces the first principal surface of the second substrate and the first wiring structure is coupled to the second wiring structure, and
the black level calibration area comprises:
a dark current sensing circuit including one or more photo diodes disposed in the first substrate;
a first seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view;
a second seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first seal ring structure and the second seal ring structure; and
an opaque cover layer disposed over the first principal surface and covering the dark current sensing circuit, the first seal ring structure and the second seal ring structure.
10 . The CMOS image sensor of claim 9 , wherein the black level calibration area comprises:
first trench isolation structures extending from the first principal surface of the first substrate to an inside the first substrate and disposed between the opaque cover layer and the first and second seal ring structures.
11 . The CMOS image sensor of claim 10 , wherein the black level calibration area comprises:
second trench isolation structures extending from the first principal surface of the first substrate to an inside the first substrate and disposed between the opaque cover layer and the dark current sensing circuit.
12 . The CMOS image sensor of claim 9 , wherein the second semiconductor circuit includes:
a third seal ring structure disposed over the second substrate and coupled to the first seal ring structure; and
a fourth seal ring structure disposed over the second substrate and coupled to the second seal ring structure.
13 . The CMOS image sensor of claim 9 , wherein the opaque cover layer is made of tungsten or an alloy of tungsten.
14 . The CMOS image sensor of claim 9 , wherein the opaque cover layer includes a first layer made of tungsten or an alloy of tungsten and a second layer disposed over the first layer and made of a dielectric material.
15 . A complementary metal-oxide-semiconductor (CMOS) image sensor, comprising:
a substrate having a first principal surface and a second principal surface opposite to the first principal surface;
an image pixel area including a plurality of photo diodes disposed in the substrate and a plurality of color filters disposed over the first principal surface of the substrate; and
a black level calibration area adjacent to the image pixel area for determining a dark voltage current, wherein:
the black level calibration area comprises:
a dark current sensing circuit including one or more photo diodes disposed in the substrate;
a first seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view;
a second seal ring structure disposed over the second principal surface and surrounding the image pixel area in plan view;
a first barrier structure disposed over the second principal surface;
a second barrier structure disposed over the second principal surface;
an opaque cover layer disposed over the first principal surface and covering the dark current sensing circuit, the first seal ring structure, the second seal ring structure, the first barrier structure and the second barrier structure; and
first trench isolation structures extending from the first principal surface to an inside the substrate and disposed between the opaque cover layer and the first and second seal ring structures, and
the dark current sensing circuit is disposed between the first seal ring structure and the second seal ring structure and between the first barrier structure and the second barrier structure in plan view.
16 . The CMOS image sensor of claim 15 , wherein the black level calibration area comprises:
second trench isolation structures extending from the second principal surface to the inside the substrate and disposed between the opaque cover layer and the first and second seal ring structures.
17 . The CMOS image sensor of claim 16 , wherein the black level calibration area comprises:
third trench isolation structures extending from the first principal surface to the inside the substrate and disposed between the opaque cover layer and the first and second barrier structures.
18 . The CMOS image sensor of claim 17 , wherein the black level calibration area comprises:
fourth trench isolation structures extending from the first principal surface to the inside the substrate and disposed between the opaque cover layer and the first and second barrier structures.
19 . The CMOS image sensor of claim 15 , wherein each of the first seal ring structure, the second seal ring structure, the first barrier structure and the second barrier structure includes conductive wiring patterns and one or more vias coupling adjacent wiring patterns.
20 . The CMOS image sensor of claim 15 , wherein a width in plan view of each of the first seal ring structure, the second seal ring structure, the first barrier structure and the second barrier structure is in a range from 10 μm to 40 μm.