IP Library › Granted Patent US 12,648,413
Granted Patent B2
US 12,648,413 · App. 18/163,274 · Granted Jun 2, 2026

Method of manufacturing semiconductor device

Inventor: Ping-Lung Yu (Taichung City, TW)
Assignee: Winbond Electronics Corp.
H10P76/4085H10B41/30H10P30/40H10P32/20H10P50/283
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Quick Facts
Patent No.
US 12,648,413
App. No.
18/163,274
Granted
Jun 2, 2026
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes the following. A core material layer and a patterned mask layer are formed above a target layer. A first spacer layer is formed and a first treatment process is performed to form a treated first spacer layer. A first removal process is performed on the treated first spacer layer and the patterned mask layer to form multiple first spacers. The core material layer is patterned to form a core layer using the first spacers as a mask. A second spacer layer is formed and a second treatment process is performed to form a treated second spacer layer. A second removal process is performed on the treated second spacer layer and the core layer to form multiple second spacers. A pattern of the second spacers is transferred to the target layer to form a patterned target layer.

Claims (43)

1 . A method of manufacturing a semiconductor device, comprising:

forming a core material layer above a target layer;

forming a patterned mask layer on the core material layer;

forming a first spacer layer to cover the patterned mask layer and the core material layer;

performing a first treatment process to form a treated first spacer layer;

performing a first removal process on the treated first spacer layer and the patterned mask layer to form a plurality of first spacers;

patterning the core material layer to form a core layer using the first spacers as a mask;

forming a second spacer layer to cover the core layer;

performing a second treatment process to form a treated second spacer layer, wherein during the second treatment process, a part of the second spacer layer remains covering the core layer;

performing a second removal process on the treated second spacer layer and the core layer to form a plurality of second spacers; and

transferring a pattern of the second spacers to the target layer to form a patterned target layer.

2 . The method of manufacturing the semiconductor device according to claim 1 , wherein a material of the first spacer layer and the second spacer layer comprises a dielectric material.

3 . The method of manufacturing the semiconductor device according to claim 1 , wherein density of the treated first spacer layer is higher than density of the first spacer layer.

4 . The method of manufacturing the semiconductor device according to claim 1 , wherein density of the treated second spacer layer is higher than density of the second spacer layer.

5 . The method of manufacturing the semiconductor device according to claim 1 , wherein hardness of the treated first spacer layer is higher than hardness of the first spacer layer.

6 . The method of manufacturing the semiconductor device according to claim 1 , wherein hardness of the treated second spacer layer is higher than hardness of the second spacer layer.

7 . The method of manufacturing the semiconductor device according to claim 1 , wherein hydrophilicity of the treated first spacer layer is different from hydrophilicity of the first spacer layer.

8 . The method of manufacturing the semiconductor device according to claim 1 , wherein hydrophilicity of the treated second spacer layer is different from hydrophilicity of the second spacer layer.

9 . The method of manufacturing the semiconductor device according to claim 1 , wherein dosage of the second treatment process is greater than dosage of the first treatment process.

10 . The method of manufacturing the semiconductor device according to claim 1 further comprising:

forming a sacrificial layer on the target layer; and

forming a hard mask layer on the target layer,

wherein transferring the pattern of the second spacers to the target layer to form the patterned target layer comprises:

patterning the hard mask layer and the sacrificial layer to form a patterned hard mask layer and a patterned sacrificial layer using the second spacers as a mask; and

patterning the target layer to form the patterned target layer using the patterned hard mask layer as a mask.

11 . The method of manufacturing the semiconductor device according to claim 1 , wherein the first treatment process comprises a plasma treatment process or an ion implantation process.

12 . The method of manufacturing the semiconductor device according to claim 1 , wherein the second treatment process comprises a plasma treatment process or an ion implantation process.

13 . A method of manufacturing a semiconductor device, comprising:

forming a core material layer above a target layer;

forming a patterned mask layer on the core material layer;

forming a first spacer layer to cover the patterned mask layer and the core material layer;

performing a first removal process on the first spacer layer and the patterned mask layer to form a plurality of first spacers;

patterning the core material layer to form a core layer using the first spacers as a mask;

forming a second spacer layer to cover the core layer;

performing a first treatment process to change a property of the second spacer layer and to form a treated second spacer layer, wherein during the first treatment process, a part of the second spacer layer remains covering the core layer;

performing a second removal process on the treated second spacer layer and the core layer to form a plurality of second spacers; and

transferring a pattern of the second spacers to the target layer to form a patterned target layer.

14 . The method of manufacturing the semiconductor device according to claim 13 , further comprising performing a second treatment process to change a property of the first spacer layer and to form a treated first spacer layer, wherein density of the treated first spacer layer is higher than density of the first spacer layer.

15 . The method of manufacturing the semiconductor device according to claim 13 , wherein density of the treated second spacer layer is higher than density of the second spacer layer.

16 . The method of manufacturing the semiconductor device according to claim 14 , wherein hardness of the treated first spacer layer is higher than hardness of the first spacer layer.

17 . The method of manufacturing the semiconductor device according to claim 13 , wherein hardness of the treated second spacer layer is higher than hardness of the second spacer layer.

18 . The method of manufacturing the semiconductor device according to claim 14 , wherein hydrophilicity of the treated first spacer layer is different from hydrophilicity of the first spacer layer.

19 . The method of manufacturing the semiconductor device according to claim 13 , wherein hydrophilicity of the treated second spacer layer is different from hydrophilicity of the second spacer layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2023
From: YU, PING-LUNG
To: WINBOND ELECTRONICS CORP.
Reel/Frame 062566/0774 →
Priority Claims (1)
TW 111123985 · Jun 28, 2022 · national
Continuity (1)
Related Publication 20230420255A1 · Dec 28, 2023
References Cited (6)
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