Semiconductor packages having upper conductive patterns
A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer, a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, first upper conductive patterns disposed on the base layer, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad, a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate, an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip, and an upper redistribution structure on the encapsulant. The upper redistribution structure includes a redistribution via connected to the second upper conductive pattern.
1 . A semiconductor package comprising:
a lower redistribution structure including a wiring layer, and vias connected to the wiring layer;
a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, a first set of first upper conductive patterns disposed on the base layer, a second set of first upper conductive patterns disposed on the base layer, each of the first set of first upper conductive patterns including an upper pad, and second upper conductive patterns disposed on and in contact with the upper pads of the first set of first upper conductive patterns;
a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate;
an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip; and
an upper redistribution structure on the encapsulant,
wherein the upper redistribution structure includes a plurality of redistribution vias, each of the plurality of redistribution vias extend below an upper surface of the encapsulant and connect to an upper surface of the second upper conductive patterns,
wherein the upper surface of the second upper conductive patterns and the upper pads are disposed below the upper surface of the encapsulant,
wherein each of the second set of first upper conductive patterns includes an upper wiring having a smaller horizontal width than the upper pads of the first set of first upper conductive patterns,
wherein the entirety of a top surface of the upper wirings of the second set of first upper conductive patterns are in contact with the encapsulant, and
wherein a bottom surface of the upper pads is disposed above a top surface of the base layer.
2 . The semiconductor package according to claim 1 , wherein:
with respect to a top down view, the outer boundary of the second upper conductive patterns do not extend outside the outer boundary of the upper pads; and
only a part of an upper surface of the upper pads contact the encapsulant.
3 . The semiconductor package according to claim 1 , wherein:
the connection substrate further includes upper vias; and
the upper vias are disposed below and in contact with the upper pads, vertically extend through the base layer, and are electrically connected to the lower conductive patterns.
4 . The semiconductor package according to claim 3 , wherein the connection substrate further includes a seed layer covering a lower surface of the upper pads and a lower surface and side surfaces of the upper vias.
5 . The semiconductor package according to claim 4 , wherein the seed layer contacts at least one of the lower conductive patterns.
6 . The semiconductor package according to claim 1 , wherein a height of each of the second upper conductive patterns is 15 to 20 μm.
7 . The semiconductor package according to claim 2 ,
wherein no side surface of the second upper conductive patterns are in contact with a wiring or any other conductive material.
8 . The semiconductor package according to claim 1 , wherein:
the upper redistribution structure further includes an insulating layer covering the upper surface of the encapsulant, and wiring layers on the insulating layer; and
at least one of the wiring layers is connected to the plurality of redistribution vias.
9 . The semiconductor package according to claim 8 , wherein a height between an upper surface of the insulating layer and the upper surface of the second upper conductive patterns is 25 to 35 μm.
10 . The semiconductor package according to claim 9 , wherein the upper redistribution structure further includes a seed layer covering a lower surface of the wiring layers and a lower surface and side surfaces of the redistribution vias, and
wherein the seed layer is disposed between and in contact with the lower surface of the redistribution vias and the upper surface of the second upper conductive patterns.
11 . The semiconductor package according to claim 1 , wherein a horizontal width of the second upper conductive patterns is equal to a horizontal width of the upper pads.
12 . The semiconductor package according to claim 1 , wherein the lower redistribution structure is electrically connected to the semiconductor chip and the connection substrate.
13 . A semiconductor package comprising:
a lower package; and
an upper package on the lower package,
wherein the lower package includes
a lower redistribution structure including a wiring layer, and vias connected to the wiring layer,
a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, a first set of first upper conductive patterns disposed on the base layer, a second set of first upper conductive patterns disposed on the base layer, each of the first set of first upper conductive patterns including an upper pad, and second upper conductive patterns disposed on and in contact with the upper pads of the first set of first upper conductive patterns,
a first semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate,
an encapsulant covering the lower redistribution structure, the connection substrate and the first semiconductor chip, and
an upper redistribution structure on the encapsulant,
wherein the upper redistribution structure includes a plurality of redistribution vias, each of the plurality of redistribution vias extend below an upper surface of the encapsulant and connect to an upper surface of the second upper conductive patterns,
wherein the upper surface of the second upper conductive patterns and the upper pads are disposed below the upper surface of the encapsulant,
wherein each of the second set of first upper conductive patterns includes an upper wiring having a smaller horizontal width than the upper pads of the first set of first upper conductive patterns,
wherein the entirety of a top surface of the upper wirings of the second set of first upper conductive patterns are in contact with the encapsulant, and
wherein a bottom surface of the upper pads is disposed above a top surface of the base layer.
14 . The semiconductor package according to claim 13 , wherein:
the upper package includes
a substrate,
a package connection terminal disposed below the substrate and connected to the upper redistribution structure, and
a second semiconductor chip on the substrate; and
the second semiconductor chip is electrically connected to the lower redistribution structure via the substrate, the package connection terminal, the upper redistribution structure and the connection substrate.
15 . The semiconductor package according to claim 14 , wherein the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.
16 . A semiconductor package comprising:
a lower redistribution structure including a wiring layer, and a vias connected to the wiring layer;
an outer connection terminal below the lower redistribution structure;
a connection substrate on the lower redistribution structure, the connection substrate including base layers, lower conductive patterns in the base layers, a first set of first upper conductive patterns disposed on an uppermost one of the base layers, a second set of first upper conductive patterns disposed on the uppermost one of the base layers, each of the first set of first upper conductive patterns and the second set of first upper conductive patterns including an upper pad, and second upper conductive patterns disposed only on and in contact with the upper pads of the first set of first upper conductive patterns;
a semiconductor chip disposed on the lower redistribution structure and disposed In a cavity of the connection substrate;
an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip; and
an upper redistribution structure on the encapsulant,
wherein the upper redistribution structure includes an insulating layer covering an upper surface of the encapsulant, a wiring layer on the insulating layer, and a plurality of redistribution vias interconnecting the wiring layer and the second upper conductive patterns,
wherein each of the redistribution vias extend below an upper surface of the encapsulant and connect to an upper surface of the second upper conductive patterns,
wherein the upper surface of the second upper conductive patterns and the upper pads are disposed below the upper surface of the encapsulant,
wherein each of the second set of first upper conductive patterns includes an upper wiring having a smaller horizontal width than the upper pads of the first set of first upper conductive patterns,
wherein the entirety of a top surface of the upper wirings of the second set of first upper conductive patterns are in contact with the encapsulant, and
wherein a bottom surface of the upper pad is disposed above a top surface of the base layer.
17 . The semiconductor package according to claim 16 , wherein the connection substrate further includes connection vias interconnecting the lower conductive patterns of different layers.