Semiconductor package including buffer chip bonded to memory dies using wires
A buffer chip is wire-bonded to memory dies. A semiconductor package includes a semiconductor die stack, a first set of wire bonds connected to a first set of semiconductor dies, a second set of wire bonds connected to a second set of semiconductor dies, and the buffer chip. The second set of semiconductor dies are on the first set of semiconductor dies. The buffer chip includes a first set of die bond pads being close to the semiconductor die stack, and a second set of die bond pads being distant from the semiconductor die stack. The second set of wire bonds extends to the first set of die bond pads of the buffer chip, and the first set of wire bonds extends to the second set of die bond pads of the buffer chip.
1 . A semiconductor package comprising:
a package substrate;
a semiconductor die stack which is mounted on the package substrate and in which one or more semiconductor dies are stacked, the semiconductor die stack including a first set of semiconductor dies and a second set of semiconductor dies on the first set of semiconductor dies;
a first set of wire bonds connecting the first set of semiconductor dies to each other;
a second set of wire bonds connecting the second set of semiconductor dies to each other; and
a buffer chip mounted on the package substrate and including a first set of die bond pads and a second set of die bond pads, the first set of die bond pads being close to the semiconductor die stack, the second set of die bond pads being distant from the semiconductor die stack,
wherein the second set of wire bonds is connected to the first set of die bond pads of the buffer chip, and the first set of wire bonds is connected to the second set of die bond pads of the buffer chip.
2 . The semiconductor package as claimed in claim 1 , wherein the buffer chip is on the package substrate at a distance from the semiconductor die stack, and
the package substrate includes bond fingers between the buffer chip and the semiconductor die stack.
3 . The semiconductor package as claimed in claim 2 , wherein the second set of wire bonds is partially bonded to the bond fingers and is connected to the first set of die bond pads of the buffer chip.
4 . The semiconductor package as claimed in claim 2 , further comprising a third set of wire bonds connecting the first set of semiconductor dies and the second set of semiconductor dies to each other,
wherein the buffer chip further includes a third set of die bond pads providing ground voltage, and
the third set of wire bonds is connected to the third set of die bond pads of the buffer chip.
5 . The semiconductor package as claimed in claim 4 , wherein the third set of wire bonds is partially bonded to the bond fingers and is connected to the third set of die bond pads of the buffer chip.
6 . The semiconductor package as claimed in claim 1 , wherein the package substrate includes a first side surface in a first direction and a second side surface opposite the first side surface, and
the one or more semiconductor dies of the semiconductor die stack are stacked in a continuous offset stepped configuration along the first side surface in the first direction.
7 . The semiconductor package as claimed in claim 6 , wherein, in the semiconductor die stack, a group of the second set of semiconductor dies is shifted from a group of the first set of semiconductor dies in a second direction perpendicular to the first direction.
8 . A semiconductor package comprising:
a package substrate;
a semiconductor die stack which is mounted on the package substrate and in which one or more semiconductor dies are stacked, the semiconductor die stack including a first set of semiconductor dies, a second set of semiconductor dies on the first set of semiconductor dies, and a third set of semiconductor dies on the second set of semiconductor dies;
a first set of wire bonds connecting the first set of semiconductor dies to each other;
a second set of wire bonds connecting the second set of semiconductor dies to each other;
a third set of wire bonds connecting the third set of semiconductor dies to each other; and
a buffer chip mounted on the package substrate and including a first set of die bond pads, a second set of die bond pads, and a third set of die bond pads, the first set of die bond pads being close to the semiconductor die stack, the second set of die bond pads being between the first set of die bond pads and the third set of die bond pads, the third set of die bond pads being distant from the semiconductor die stack,
wherein the third set of wire bonds is connected to the first set of die bond pads of the buffer chip, the second set of wire bonds is connected to the second set of die bond pads of the buffer chip, and the first set of wire bonds is connected to the third set of die bond pads of the buffer chip.
9 . The semiconductor package as claimed in claim 8 , wherein the buffer chip is on the package substrate at a distance from the semiconductor die stack, and
the package substrate includes bond fingers between the buffer chip and the semiconductor die stack.
10 . The semiconductor package as claimed in claim 9 , wherein the third set of wire bonds is partially bonded to the bond fingers and is connected to the first set of die bond pads of the buffer chip.
11 . The semiconductor package as claimed in claim 9 , further comprising a fourth set of wire bonds connecting the first set of semiconductor dies, the second set of semiconductor dies, and the third set of semiconductor dies to each other,
wherein the buffer chip further includes a fourth set of die bond pads providing ground voltage, and
the fourth set of wire bonds is connected to the fourth set of die bond pads of the buffer chip.
12 . The semiconductor package as claimed in claim 11 , wherein the fourth set of wire bonds is partially bonded to the bond fingers and is connected to the fourth set of die bond pads of the buffer chip.
13 . The semiconductor package as claimed in claim 8 , wherein the package substrate includes a first side surface in a first direction and a second side surface opposite the first side surface, and
the one or more semiconductor dies of the semiconductor die stack are stacked in a continuous offset stepped configuration along the first side surface in the first direction.
14 . A semiconductor package comprising:
a package substrate including a first side surface in a first direction and a second side surface opposite the first side surface;
first and second semiconductor die stacks each mounted on the package substrate and in which one or more semiconductor dies are stacked, the second semiconductor die stack being apart from the first semiconductor die stack in the first direction, the first semiconductor die stack including a first set of semiconductor dies and a second set of semiconductor dies on the first set of semiconductor dies, the second semiconductor die stack including a third set of semiconductor dies and a fourth set of semiconductor dies on the third set of semiconductor dies;
a first set of wire bonds connecting the first set of semiconductor dies to each other;
a second set of wire bonds connecting the second set of semiconductor dies to each other;
a third set of wire bonds connecting the third set of semiconductor dies to each other;
a fourth set of wire bonds connecting the fourth set of semiconductor dies to each other; and
a buffer chip mounted on the package substrate and including a first set of die bond pads, a second set of die bond pads, a third set of die bond pads, and a fourth set of die bond pads, the first set of die bond pads being close to the first semiconductor die stack, the second set of die bond pads being distant from the first semiconductor die stack, the third set of die bond pads being close to the second semiconductor die stack, the fourth set of die bond pads being distant from the second semiconductor die stack,
wherein the second set of wire bonds is connected to the first set of die bond pads of the buffer chip, the first set of wire bonds is connected to the second set of die bond pads of the buffer chip, the fourth set of wire bonds is connected to the third set of die bond pads of the buffer chip, and the third set of wire bonds is connected to the fourth set of die bond pads of the buffer chip.
15 . The semiconductor package as claimed in claim 14 , wherein the buffer chip is on the package substrate between the first semiconductor die stack and the second semiconductor die stack, and
the package substrate includes bond fingers between the buffer chip and the first semiconductor die stack and between the buffer chip and the second semiconductor die stack.
16 . The semiconductor package as claimed in claim 15 , wherein the second set of wire bonds is partially bonded to the bond fingers and is connected to the first set of die bond pads of the buffer chip, and
the fourth set of wire bonds is partially bonded to the bond fingers and is connected to the third set of die bond pads of the buffer chip.
17 . The semiconductor package as claimed in claim 15 , further comprising:
a fifth set of wire bonds connecting the first set of semiconductor dies and the second set of semiconductor dies to each other; and
a sixth set of wire bonds connecting the third set of semiconductor dies and the fourth set of semiconductor dies to each other,
wherein the buffer chip further includes a fifth set of die bond pads providing ground voltage, and
the fifth set of wire bonds and the sixth set of wire bonds each extend to be connected to the fifth set of die bond pads of the buffer chip.
18 . The semiconductor package as claimed in claim 17 , wherein the fifth set of wire bonds and the sixth set of wire bonds are partially bonded to the bond fingers and each extend to be connected to the fifth set of die bond pads of the buffer chip.
19 . The semiconductor package as claimed in claim 14 , wherein the one or more semiconductor dies of the first semiconductor die stack are stacked in a continuous offset stepped configuration along the first side surface in the first direction, and
the one or more semiconductor dies of the second semiconductor die stack are stacked in a continuous offset stepped configuration along the second side surface in the first direction.
20 . The semiconductor package as claimed in claim 14 , wherein, in the first semiconductor die stack, a group of the second set of semiconductor dies is shifted from a group of the first set of semiconductor dies in a second direction perpendicular to the first direction, and
in the second semiconductor die stack, a group of the fourth set of semiconductor dies is shifted from a group of the third set of semiconductor dies in the second direction.