Granted Patent B2

US 12,650,465 · App. 18/500,337 · Granted Jun 9, 2026

Inventor: Cameron Mcnairy (Fort Collins, CO)

Assignee: SiFive, Inc.

G01R31/31703G01R31/31726

Abstract

Claims (54)

1 . An apparatus comprising:

a first circuitry configured to:

generate a first output based on an input, and

generate a signal, separate from the first output, indicating a detection of an error associated with the first output;

a second circuitry configured to generate a second output based on the input; and

a wrapper circuitry configured to:

receive the first output and the second output;

after receiving the first output and the second output, receive the signal indicating the detection of the error associated with the first output;

between (i) receiving the first output and the second output and (ii) receiving the signal indicating the detection of the error associated with the first output, compare the first output and the second output to perform a check for correctness; and

responsive to receipt of the signal indicating the detection of the error associated with the first output, select the second output from the second circuitry as a system output and disable the check for correctness.

2 . The apparatus of claim 1 , wherein the second circuitry is configured to generate a second signal, separate from the second output, indicating a detection of a second error associated with the second output, and wherein the wrapper circuitry is configured to, responsive to receipt of the second signal, ignore the check for correctness.

3 . The apparatus of claim 1 , wherein the wrapper circuitry provides the system output from the second circuitry to avoid a deadlock resulting from transaction suppression due to a difference between the first output and the second output.

4 . The apparatus of claim 1 , wherein the first circuitry is a first processor core, and the second circuitry is a second processor core.

5 . The apparatus of claim 1 , wherein the first circuitry is a first functional unit implemented by a processor core, and the second circuitry is a second functional unit implemented by the processor core.

6 . The apparatus of claim 1 , wherein the first circuitry is a first system on a chip (SoC), and the second circuitry is a second SoC.

7 . The apparatus of claim 1 , wherein the error associated with the first output is detected using at least one of an error correction code (ECC), a parity bit, a checksum, or a cyclic redundancy check (CRC).

8 . The apparatus of claim 1 , wherein the wrapper circuitry saves state information associated with the second circuitry when the first circuitry sends the signal indicating the detection of the error associated with the first output, the state information enabling a synchronization between the first circuitry and the second circuitry.

9 . The apparatus of claim 1 , further comprising:

an injection circuitry connected to the first circuitry, wherein the injection circuitry is configured to inject a signal to cause the error associated with the first output.

10 . The apparatus of claim 1 , further comprising:

a first delay element to delay the input to the first circuitry so that the input is received by the first circuitry later than the input is received by the second circuitry, and a second delay element to delay the second output so that the first output and the second output are synchronized, wherein the wrapper circuitry is configured to inject a signal in the first delay element to cause the error associated with the first output.

11 . The apparatus of claim 1 , wherein the check for correctness is performed by comparing the first output to the second output to detect a difference between the first output and the second output.

12 . The apparatus of claim 1 , wherein the first circuitry and the second circuitry are configured to operate in lockstep with the first circuitry initially operating as a master and the second circuitry initially operating as a checker.

13 . The apparatus of claim 1 , wherein the wrapper circuitry is configured to initially select the first output as the system output and use the second output to check for correctness of the first output.

14 . The apparatus of claim 1 , wherein the first circuitry includes a processor core with multiple pipeline stages and the error associated with the first output is detected in an earlier pipeline stage before a later pipeline stage that writes data to generate the first output.

15 . A method comprising:

generating, by a first circuitry, a first output based on an input;

generating, by the first circuitry, a signal, separate from the first output, indicating a detection of an error associated with the first output;

sending, by the first circuitry, the signal indicating the detection of the error associated with the first output;

generating, by a second circuitry, a second output based on the input;

prior to receipt of the signal indicating the detection of the error associated with the first output, comparing the first output and the second output to perform a check for correctness; and

responsive to receipt of the signal indicating the detection of the error associated with the first output, selecting the second output from the second circuitry as a system output and disabling the check for correctness.

16 . The method of claim 15 , further comprising:

generating, by the second circuitry, a second signal, separate from the second output, indicating a detection of a second error associated with the second output; and

ignoring, responsive to receipt of the second signal, the check for correctness until a synchronization event between the first circuitry and the second circuitry.

17 . The method of claim 15 , further comprising:

saving, state information associated with the second circuitry when the first circuitry sends the signal indicating the detection of the error associated with the first output; and

synchronizing between the first circuitry and the second circuitry using the state information.

18 . The method of claim 15 , further comprising:

delaying the input to the first circuitry so that the input is received by the first circuitry later than the input is received by the second circuitry;

delaying the second output so that the first output and the second output are synchronized; and

injecting a signal in a delay element, used to delay the input to the first circuitry, to cause the error.

19 . The method of claim 15 , further comprising:

operating the first circuitry and the second circuitry in lockstep with the first circuitry initially operating as a master and the second circuitry initially operating as a checker.

20 . A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:

a first circuitry configured to:

generate a first output based on an input, and

generate a signal, separate from the first output, indicating a detection of an error associated with the first output;

a second circuitry configured to generate a second output based on the input; and

a wrapper circuitry configured to:

receive the first output and the second output;

after receiving the first output and the second output, receive the signal indicating the detection of the error associated with the first output;

between (i) receiving the first output and the second output and (ii) receiving the signal indicating the detection of the error associated with the first output, compare the first output and the second output to perform a check for correctness; and

responsive to receipt of the signal indicating the detection of the error associated with the first output, select the second output from the second circuitry as a system output and disable the check for correctness.

Assignments (1)

Continuity (2)

References Cited (9)