Quantum device, method for reading the state of charge, method for determining a stability diagram and method for determining spin correlations
A semiconductor device includes a layer of a semiconductor material in which is formed an active zone; a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in part the active zone; a plurality of second gates forming a plurality of columns; at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, and a first electrode and a second electrode situated on either side of the plurality of measurement gates in the active zone.
1 . A semiconductor device, comprising:
a layer of a semiconductor material in which is formed an active zone;
a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in a part of the active zone;
a plurality of second gates forming a plurality of columns, lines of the plurality of lines intersecting the columns of the plurality of columns while covering in the part of the active zone and being electrically isolated from the plurality of lines, an intersection of two successive lines with two successive columns delimiting an island so as to obtain a plurality of islands spread out on a plurality of chains of islands, the plurality of chains of islands being arranged along an axis parallel to the lines of the plurality of lines, each chain of islands of the plurality of chains of islands comprising a plurality of islands, a first end materialized by a first extreme column and a second end materialized by a second extreme column;
at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, end of the designated measurement gate closest to the second extreme column being situated in the active zone, the at least one third gate or gates being configured to realize one or more measurement means arranged so as to be able to measure the charge state of the island situated at the level of the second end of each chain of islands;
a first electrode and a second electrode situated on either side of the designated measurement gate or gates in the active zone and configured such that a current going from the first electrode to the second electrode passes between the designated measurement gate or gates and the second extreme column.
2 . The semiconductor device according to claim 1 , wherein a third measurement electrode is situated facing each chain of islands of the plurality of chains of islands.
3 . The semiconductor device according to claim 1 , comprising a plurality of fourth gates, each fourth gate of the plurality of fourth gates being situated in an island such that each island of the plurality of islands comprises the fourth gate of the plurality of fourth gates.
4 . The semiconductor device according to claim 2 , further comprising a plurality of measurement gates and a plurality of fourth electrodes, each fourth electrode of the plurality of fourth electrodes being situated in the active zone, between two successive measurement gates of the plurality of measurement gates.
5 . The semiconductor device according to claim 4 , wherein the active zone comprises a plurality of fingers, a measurement gate of the plurality of measurement gates being situated between each finger of the plurality of fingers, fingers of the plurality of fingers being connected together by a common part, the end of the plurality of measurement gates closest to the first extreme column being situated on said common part, the first electrode being situated on a first extreme finger of the plurality of fingers, the second electrode being situated on a second extreme finger of the plurality of fingers, each finger of the plurality of fingers comprised between two measurement gates comprising a fourth electrode of the plurality of fourth electrodes.
6 . The semiconductor device according to claim 5 , wherein each finger of the plurality of fingers has an index, indices being attributed in an increasing and continuous manner between the first extreme finger and the second extreme finger, a length of the plurality of fingers having an even index being different from the length of the plurality of fingers having an odd index.
7 . The semiconductor device according to claim 1 , wherein the layer of the semiconductor material comprising the active zone comprises openings over an entirety of a thickness thereof, said openings being situated under each intersection of a line of the plurality of lines with a column of the plurality of columns.
8 . A method for reading the charge state of the quantum dots of at least one line of the quantum dots of the semiconductor device according to claim 1 , each island of the semiconductor device being configured to form a quantum dot, each chain of islands thus forming a line of the quantum dots and each island of the second extreme column forming an extreme quantum dot, the method comprising, for at least one line of the quantum dots:
a first step of determining the charge state of the extreme quantum dot of the considered line using the one or more measurement means for measuring the charge state associated with the considered line;
a second step of discharging the charged particles present in the extreme quantum dot;
for each quantum dot of the considered line of the quantum dots and starting from the quantum dot the closest to the extreme quantum dot, a third step of transfer of the charge state from the considered quantum dot to the quantum dot adjacent to the considered quantum dot the closest to the extreme quantum dot;
the first, second and third steps being reiterated a number of times equal to the number of the quantum dots of the considered line of the quantum dots.
9 . The method according to claim 8 , wherein the first, second and third steps of the method are carried out sequentially on the lines of the quantum dots of the semiconductor device.
10 . The method according to claim 9 , wherein the first, second and third steps of the method are carried out simultaneously on the lines of the quantum dots of the semiconductor device.
11 . A method for determining the stability diagram of a quantum device, each island of the quantum device being configured to form a quantum dot, each chain of islands thus forming a line of quantum dots and each island of the second extreme column forming an extreme quantum dot, each quantum dot being separated from adjacent quantum dots by a potential barrier, the method comprising:
a first step of introduction of a plurality of charged particles into the quantum device;
a second step of application of a set of voltages on the plurality of gates;
a third step of placement of each of the quantum dots in a regime such that the potential barrier separating each quantum dot from the adjacent quantum dots is configured such that the charged particle or particles contained in the considered quantum dot cannot traverse the potential barrier to be displaced to the quantum dots adjacent to said quantum dot even when such a transition is allowed from an energy viewpoint, designated completely isolated regime;
a fourth step of implementing a method according to claim 8 on all the lines of quantum dots of the quantum device so as to determine the charge state of each quantum dot for the set of applied voltages, the isolated regime only being lifted during the transfer of charged particles from one quantum dot to the adjacent quantum dot, the lifting of the isolated regime only concerning the quantum dots concerned by the transfer;
the first, second, third and fourth steps being repeated for a plurality of sets of voltages so as to determine the stability diagram of the quantum device.
12 . A method for determining the spin state of a plurality of spin carrying charged particles contained in the quantum dots of a device, each island of the device being configured to form a quantum dot, each chain of islands thus forming a line of quantum dots and each island of the second extreme column forming an extreme quantum dot, the method comprising:
a first step of initialization of the charge state of the quantum dots such that each quantum dot contains a single charged particle;
a second step of formation of a plurality of pairs of adjacent quantum dots, a quantum dot only being able to belong to a single pair of adjacent quantum dots;
for each pair of adjacent quantum dots, a third step of spin/charge conversion such that the charge state of the pair of the quantum dots is dependent on the initial spin state of the charged particles contained in said pair;
a fourth step of implementing a method according to claim 8 so as to determine the charge state of each quantum dot and thus the spin state associated with each pair of the quantum dots;
the first, second, third and fourth steps being repeated until the spin state of all the pairs of adjacent quantum dots that it is possible of form has been determined.
13 . A method for manufacturing a semiconductor device according to claim 1 from a substrate comprising a semiconductor stack, the method comprising:
a step of lithography so as to define a pattern associated with an active zone on the semiconductor stack and on the dielectric layer present on the semiconductor stack when such a dielectric layer has been deposited beforehand;
a step of etching of the semiconductor stack according to the pattern associated with the active zone defined during the preceding lithography step;
a step of depositing a first gate stack comprising a second dielectric layer and a first layer of a conductive material;
a step of depositing a hard mask on the gate stack;
a step of lithography so as to define a pattern associated with the pluralities of first gates and measurement gates;
a step of etching of the hard mask according to the pattern defined during the preceding lithography step so as to transfer said pattern into the hard mask;
a step of etching of the gate stack according to the pattern defined during the preceding lithography step and transferred to the hard mask;
a step of depositing a third dielectric layer on the structure obtained at the end of the preceding etching step;
a step of depositing a second layer of a conductive material on the third dielectric layer so as to form with the latter a second gate stack;
a step of depositing a hard mask on the second gate stack;
a step of lithography so as to define a pattern associated with the plurality of second gates;
a step of etching of the hard mask according to the pattern defined during the preceding lithography step so as to transfer said pattern into the hard mask;
a step of etching of the second gate stack according to the pattern defined during the preceding lithography step and transferred to the hard mask.
14 . The method according to claim 13 comprising, at the end of the step of etching according to the pattern associated with the active zone, a step of realizing microstructures in the semiconductor stack at the level of the active zone.
15 . A method according to claim 14 , wherein the step of realizing microstructures in the semiconductor stack comprises:
a step of depositing a hard mask on the structure obtained at the end of the preceding step, the hard mask comprising a first layer of hard mask and a second layer of hard mask arranged on the first layer of hard mask;
a step of lithography so as to define a pattern associated with a plurality of lines parallel to each other;
a step of etching according to the pattern associated with the plurality of lines defined during the preceding lithography step, the etching being carried out over the entire thickness of the second layer of hard mask so as to expose a part of the first layer of hard mask;
a step of lithography so as to define a pattern associated with a plurality of columns parallel to each other, the columns of the plurality of columns intersecting the lines of the plurality of lines, a portion of the exposed part of the first layer of hard mask remaining exposed at the end of this step;
a step of etching according to the pattern associated with the plurality of columns defined during the preceding lithography step, the etching being carried out over the entire thickness of the first layer of the hard mask so as to etch entirely the portion of the first layer of hard mask that remained exposed and thus to define a matrix of parallelogram patterns in the first layer of hard mask;
a step of selective removal of the second layer of the hard mask;
a step of etching of the semiconductor stack according to the patterns formed in the first layer of the hard mask;
a step of selective removal of the first layer of hard mask.
16 . The method according to claim 15 , wherein the associated microstructure patterns are integrated during the lithography step so as to define a pattern associated with an active zone and the step of realizing microstructures is implemented during the step of etching of the active zone according to said pattern.
17 . The method according to claim 13 , comprising, before all other steps, a step of depositing a first layer of silicon oxide on the semiconductor stack.
18 . The method according to claim 13 , comprising, at the end of the step of depositing the second gate stack, a step of planarization of the gate stack at the level of the layer of a conductive material of said stack.