Multiple input serial adder
Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.
1 . A programmable device, comprising:
a first processing unit, a second processing unit, and a programmable interconnect, wherein the first processing unit and the second processing unit are connected to the programmable interconnect;
the first processing unit and the second processing unit each comprising a plurality of full adder circuits configured to collectively receive at least three serial inputs and produce a single serial output that is a summation of the at least three serial inputs, wherein a carried state is maintained among the plurality of full adder circuits;
the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, wherein the programmable interconnect is configured to receive, from the plurality of full adder circuits of the first processing unit, the single serial output and output, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
2 . The programmable device of claim 1 , wherein a number of inputs of the processing units are equal to one more than the number of full adder circuits of the plurality.
3 . The programmable device of claim 1 , wherein each serial input is a multiple bit input.
4 . The programmable device of claim 1 , wherein each full adder circuit comprises three single bit inputs, a sum output, and a carry output.
5 . The programmable device of claim 4 , wherein the sum output of one of the plurality of full adder circuits is an input of another full adder circuit.
6 . The programmable device of claim 4 , wherein the carry output of one of the plurality of full adder circuits is retained in a register to be applied as a carry input of the full adder circuit in a subsequent cycle.
7 . The programmable device of claim 4 , wherein the carry output of one of the plurality of full adder circuits is an input of another full adder circuit.
8 . The programmable device of claim 1 , wherein the programmable interconnect further comprises a multiplexer.
9 . The programmable device of claim 1 , wherein the programmable interconnect further comprises one or more registers.
10 . A method for operating a programmable device, the programmable device comprising a first processing unit and a second processing unit coupled to a programmable interconnect, the first processing unit and second processing unit each comprising a plurality of full adder circuits and the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, the method comprising:
collectively receiving, with the plurality of full adder circuits, at least three serial inputs;
producing, with the plurality of full adder circuits, a single serial output that is a summation of the at least three serial inputs;
maintaining a carried state among the plurality of full adder circuits;
receiving, from the plurality of full adder circuits of the first processing unit, the single serial output; and
outputting, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
11 . The method of claim 10 , wherein a number of inputs of the processing units are equal to one more than the number of full adder circuits of the plurality.
12 . The method of claim 10 , wherein each full adder circuit comprises three single bit inputs, a sum output, and a carry output.
13 . The method of claim 12 , further comprising inputting the sum output of one of the plurality of full adder circuits to another full adder circuit.
14 . The method of claim 12 , further comprising retaining the carry output of one of the plurality of full adder circuits in a register to be applied as a carry input of the full adder circuit in a subsequent cycle.
15 . The method of claim 12 , further comprising inputting the carry output of one of the plurality of full adder circuits to another full adder circuit.
16 . A non-transitory computer readable medium for storing instructions that, when executed by a programmable device, the programmable device comprising a first processing unit and a second processing unit coupled to a programmable interconnect, the first processing unit and second processing unit each comprising a plurality of full adder circuits and the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, causes the programmable device to perform operations comprising:
collectively receiving, with a plurality of full adder circuits, at least three serial inputs;
producing, with the plurality of full adder circuits, a single serial output that is a summation of the at least three serial inputs;
maintaining a carried state among the plurality of full adder circuits;
receiving, from the plurality of full adder circuits of the first processing unit, the single serial output; and
outputting, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
17 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise inputting a sum output of one of the plurality of full adder circuits to another full adder circuit.
18 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise retaining a carry output of one of the plurality of full adder circuits in a register to be applied as a carry input of the full adder circuit in a subsequent cycle.
19 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise inputting a carry output of one of the plurality of full adder circuits to another full adder circuit.
20 . The non-transitory computer readable medium of claim 16 , wherein the at least three serial inputs are collectively received based on a number of registers in the programmable interconnect.