IP Library › Granted Patent US 12,651,565
Granted Patent B2
US 12,651,565 · App. 18/741,773 · Granted Jun 9, 2026

Display device

Inventors: Tae-Ho Kim (Yongin-si, KR); Seung-Jun Lee (Yongin-si, KR); Yongsu Lee (Yongin-si, KR); Jaewoo Lee (Yongin-si, KR); Seung-Hwan Cho (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/3225H10K59/126H10K59/131G09G3/3233G09G2300/0426
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Quick Facts
Patent No.
US 12,651,565
App. No.
18/741,773
Granted
Jun 9, 2026
Kind
B2
Abstract

A display device including: a display panel containing pixels connected to a light emitting control line and a light emitting control driver including a light emitting control stage that provides a light emitting control signal to the pixels through the light emitting control line, wherein the light emitting control stage includes: a first light emitting control transistor including a first electrode connected to the light emitting control line, a gate electrode connected to a first light emitting control clock line, and a second electrode connected to a first node, a first power voltage line to which a first power voltage is applied; and a shielding pattern extending between the first light emitting control transistor and the first power voltage line and receiving a power voltage higher than the first power voltage.

Claims (19)

1 . A display device comprising:

a display panel containing pixels connected to a light emitting control line; and

a light emitting control driver including a light emitting control stage that provides a light emitting control signal to the pixels through the light emitting control line,

wherein the light emitting control stage includes:

a first light emitting control transistor including a first electrode configured to receive a light emitting control signal, a gate electrode connected to a first light emitting control clock line, and a second electrode connected to a first node;

a first power voltage line to which a first power voltage is applied; and

a shielding pattern disposed between the first light emitting control transistor and the first power voltage line in a layout view and receiving a power voltage higher than the first power voltage.

2 . The display device of claim 1 , wherein the light emitting control stage further includes a second power voltage line to which a second power voltage higher than the first power voltage is applied, and

the shielding pattern is connected to the second power voltage line through a contact hole.

3 . The display device of claim 2 , wherein the light emitting control stage further includes a first capacitor including a first electrode connected to the second power voltage line and a second electrode connected to a second node.

4 . The display device of claim 3 , wherein the shielding pattern is disposed on the same layer as the second electrode of the first capacitor.

5 . The display device of claim 1 , wherein the light emitting control stage further includes a second light emitting control transistor including a first electrode connected to the first power voltage line, a gate electrode connected to a third node, and a second electrode connected to a fourth node.

6 . The display device of claim 5 , wherein the shielding pattern is disposed between the second light emitting control transistor and the first power voltage line in a layout view.

7 . The display device of claim 6 , wherein the light emitting control stage further includes a third light emitting control transistor including a first electrode connected to a fifth node, a gate electrode connected to the first power voltage line, and a second electrode connected to a sixth node.

8 . The display device of claim 7 , wherein the shielding pattern is disposed between the third light emitting control transistor and the first power voltage line in a layout view.

9 . The display device of claim 1 , wherein the first power voltage line extends in a first direction, and the shielding pattern includes a first portion extending in the first direction and a second portion extending in a second direction crossing the first direction.

10 . The display device of claim 9 , wherein the light emitting control stage further includes a light emitting blocking signal line receiving a light emitting blocking signal.

11 . The display device of claim 10 , wherein the second portion of the shielding pattern partially overlaps the light emitting blocking signal line.

12 . The display device of claim 11 , wherein the first portion of the shielding pattern is disposed between the first light emitting control transistor and the first power voltage line in a layout view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2024
From: KIM, TAE-HO; LEE, SEUNG-JUN; LEE, YONGSU; LEE, JAEWOO; CHO, SEUNG-HWAN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 067711/0232 →
Priority Claims (1)
KR 10-2023-0100609 · Aug 1, 2023 · national
Continuity (1)
Related Publication 20250046242A1 · Feb 6, 2025
References Cited (3)
US 10482817B2 · Kim et al. · 2019 [cited by applicant]
US 20190005885A1 · Kim · 2019 [cited by examiner]
US 20210280140A1 · Lee · 2021 [cited by examiner]