Pixel and display device including the same
Provided herein may be a pixel including a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node, a second transistor connected between a data line and the third node, and including a gate electrode electrically connected to a first sub-gate line, a third transistor connected between a first power line, which is configured to supply a first power voltage, and the first node, and including a gate electrode electrically connected to an emission control line, a first capacitor connected between the first node and the third node, and a light-emitting element connected between the second node and a second power line, which is configured to supply a second power voltage.
1 . A pixel comprising:
a first transistor comprising a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node;
a second transistor connected between a data line and the third node, and comprising a gate electrode electrically connected to a first sub-gate line;
a third transistor connected between a first power line, which is configured to supply a first power voltage, and the first node, and comprising a gate electrode electrically connected to an emission control line;
a first capacitor connected between the first node and the third node; and
a light-emitting element connected between the second node and a second power line, which is configured to supply a second power voltage,
wherein a single frame period comprises:
an initialization period;
a compensation period;
a data write period during which the second power voltage is configured to have a second voltage level, the third transistor is configured to be set to a turn-off state, the first transistor and the second transistor are configured to be set to a turn-on state, and a data signal having a data voltage level is configured to be supplied to the data line; and
an emission period in which the light-emitting element is configured to emit light at a luminance corresponding to current supplied from the first transistor, and during which the second power voltage is configured to have a first voltage level that is lower than the second voltage level, the second transistor is configured to be set to the turn-off state, the first transistor and the third transistor are configured to be set to the turn-on state, and a data signal having a reference voltage level, which is lower than the data voltage level, lower than the first power voltage, and higher than the first voltage level, is configured to be supplied to the data line.
2 . The pixel according to claim 1 , wherein, during the compensation period before the data write period, the third transistor is configured to be set to the turn-off state, the first transistor and the second transistor are configured to be set to the turn-on state, the data signal having the reference voltage level is configured to be supplied to the data line, and the second power voltage is configured to have the second voltage level.
3 . The pixel according to claim 1 , wherein, during the initialization period before the compensation period, the first transistor, the second transistor, and the third transistor are configured to be set to the turn-on state, the data signal having the reference voltage level is configured to be supplied to the data line, and the second power voltage is configured to have the first voltage level.
4 . The pixel according to claim 1 , wherein the first capacitor comprises a metal-insulator-metal (MIM) capacitor.
5 . The pixel according to claim 1 , wherein the first capacitor comprises a metal oxide semiconductor (MOS) capacitor.
6 . The pixel according to claim 1 , further comprising a second capacitor connected between the first node and the third node.
7 . The pixel according to claim 6 , wherein the first capacitor comprises a metal-insulator-metal (MIM) capacitor, and the second capacitor comprises a metal oxide semiconductor (MOS) capacitor.
8 . The pixel according to claim 1 , wherein the first voltage level and the second voltage level are lower than the first power voltage.
9 . A display device, comprising pixels connected to gate lines, data lines, and emission control lines,
wherein one of the pixels at an i-th pixel row and at a j-th pixel column (i and j being integers) comprises:
a first transistor comprising a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node;
a second transistor connected between a j-th data line among the data lines and the third node, and configured to receive a gate signal through an i-th gate line among the gate lines;
a third transistor connected between the first node and a first power line configured to supply a first power voltage, and configured to receive an emission control signal through an i-th emission control line among the emission control lines;
a first capacitor connected between the first node and the third node; and
a light-emitting element connected between the second node and a second power line configured to supply a second power voltage,
wherein a single frame period comprises:
an initialization period;
a compensation period;
a data write period during which the second power voltage is configured to have a second voltage level, the gate signal for setting the second transistor to a turn-on state is configured to be supplied to the i-th gate line, the emission control signal for setting the third transistor to a turn-off state is configured to be supplied to the i-th emission control line, and a data signal having a data voltage level is configured to be supplied to the j-th data line; and
an emission period in which the light-emitting element is configured to emit light at a luminance corresponding to current supplied from the first transistor, and during which the second power voltage is configured to have a first voltage level that is lower than the second voltage level, the emission control signal for setting the third transistor to the turn-on state is configured to be supplied to the i-th emission control line, the gate signal for setting the second transistor to the turn-off state is configured to be supplied to the i-th gate line, and a data signal having a reference voltage level, which is lower than the data voltage level, lower than the first power voltage, and higher than the first voltage level, is configured to be supplied to the j-th data line.
10 . The display device according to claim 9 , wherein, during the compensation period before the data write period, the gate signal for setting the second transistor to the turn-on state is configured to be supplied to the i-th gate line, the emission control signal for setting the third transistor to the turn-off state is configured to be supplied to the i-th emission control line, and the data signal having the reference voltage level is configured to be supplied to the j-th data line.
11 . The display device according to claim 9 , wherein the first capacitor comprises a metal-insulator-metal (MIM) capacitor.
12 . The display device according to claim 9 , wherein the first capacitor comprises a metal oxide semiconductor (MOS) capacitor.
13 . The display device according to claim 9 , further comprising a second capacitor connected between the first node and the third node, and
wherein the first capacitor comprises a metal-insulator-metal (MIM) capacitor, and the second capacitor comprises a metal oxide semiconductor (MOS) capacitor.