Display substrate, driving method and display device
A display substrate includes a plurality of rows of pixel circuits; the pixel circuit includes at least one of a first light emitting control circuit, a second light emitting control circuit, and a first reset circuit; the pixel circuit also includes a light emitting element, a driving circuit, a first energy storage circuit, and a second energy storage circuit; the first light emitting control circuit controls the connection between the first node and the fourth node under the control of a first light emitting control signal; the second light emitting control circuit controls the connection the power supply voltage terminal and the first terminal of the driving circuit under the control of a second light emitting control signal; the first reset circuit controls a potential of the third node under the control of a first reset signal.
1 . A display substrate, comprising a plurality of rows of pixel circuits; wherein the pixel circuit includes at least one of a first light emitting control circuit, a second light emitting control circuit, and a first reset circuit; the pixel circuit also includes a light emitting element, a driving circuit, a first energy storage circuit, and a second energy storage circuit;
a control terminal of the driving circuit is electrically connected to a first node, a first terminal of the second energy storage circuit is electrically connected to a second node, a second terminal of the second energy storage circuit is electrically connected to a third node, a first terminal of the first energy storage circuit is electrically connected to the third node, and a second terminal of the first energy storage circuit is electrically connected to a fourth node; the first energy storage circuit and the second energy storage circuit are configured to store electrical energy;
the first light emitting control circuit is electrically connected to a first light emitting control line, the first node, and the fourth node, respectively, and is configured to control the connection between the first node and the fourth node under the control of a first light emitting control signal provided by the first light emitting control line;
the second light emitting control circuit is electrically connected to a second light emitting control line, a power supply voltage terminal, and the first terminal of the driving circuit, is configured to control the connection the power supply voltage terminal and the first terminal of the driving circuit under the control of a second light emitting control signal provided by the second light emitting control line;
the first reset circuit is electrically connected to a first reset line and the third node respectively, and is configured to control a potential of the third node under the control of a first reset signal provided by the first reset line;
the second terminal of the driving circuit is electrically connected to the light emitting element, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of the potential of the first node;
the control signal line includes at least one of the first light emitting control line, the second light emitting control line, and the first reset line;
control signal lines included in at least two rows of pixel circuits included in the plurality of rows of pixel circuits are electrically connected to each other;
wherein the pixel circuit further includes a second reset circuit;
the second reset circuit is electrically connected to a first reset line and the first node, respectively, is configured to control the potential of the first node under the control of a first reset signal; or,
the second reset circuit is electrically connected to a second reset line and the first node, respectively, is configured to control the potential of the first node under the control of a second reset signal provided by the second reset line;
wherein the first reset circuit is also electrically connected to a reference voltage terminal, and is configured to write a reference voltage into the third node under the control of the first reset signal; the reference voltage terminal is configured to provide the reference voltage; the second reset circuit is also electrically connected to the reference voltage terminal, and is configured to write the reference voltage into the first node under the control of the first reset signal; or,
the first reset circuit is also electrically connected to the reference voltage terminal, and is configured to write the reference voltage into the third node under the control of the first reset signal; the second reset circuit is also electrically connected to the third node, is configured to control the connection between the first node and the third node under the control of the first reset signal; or,
the first reset circuit is also electrically connected to an initial voltage terminal, is configured to write an initial voltage provided by the initial voltage terminal into the third node under the control of the first reset signal; the second reset circuit is also electrically connected to the power supply voltage terminal, is configured to write a power supply voltage provided by the power supply voltage terminal into the first node under the control of the first reset signal.
2 . The display substrate according to claim 1 , wherein the pixel circuit further includes a data writing-in circuit;
the data writing-in circuit is electrically connected to a scanning line, a data line and the fourth node respectively, and is configured to write a data voltage provided by the data line into the fourth node under the control of a scanning signal provided by the scanning line.
3 . The display substrate according to claim 2 , wherein the pixel circuit further comprises a third light emitting control circuit;
the third light emitting control circuit is electrically connected to the scanning line, the second node and the first electrode of the light emitting element respectively, and is configured to control the connection between the second node and a first electrode of the light emitting element under the control of the scanning signal provided by the scanning line;
a second electrode of the light emitting element is electrically connected to the first voltage terminal.
4 . The display substrate according to claim 2 , wherein the pixel circuit further comprises a third light emitting control circuit;
the third light emitting control circuit is electrically connected to a third light emitting control line, the second node and the first electrode of the light emitting element respectively, and is configured to control the connection between the second node and the first electrode of the light emitting element under the control of a third light emitting control signal provided by the third light emitting control line;
the second electrode of the light emitting element is electrically connected to the first voltage terminal.
5 . The display substrate according to claim 1 , wherein the pixel circuit further comprises a third reset circuit;
the third reset circuit is electrically connected to a second reset line, an initial voltage terminal and a first electrode of the light emitting element, respectively, and is configured to write an initial voltage provided by the initial voltage terminal into the first electrode of the light emitting element under the control of a second reset signal provided by the second reset line.
6 . The display substrate according to claim 1 , wherein the first light emitting control circuit includes a first transistor, and the second light emitting control circuit includes a second transistor;
a gate electrode of the first transistor is electrically connected to the first light emitting control line, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the fourth node;
a gate electrode of the second transistor is electrically connected to the second light emitting control line, a first electrode of the second transistor is electrically connected to the power supply voltage terminal, and a second electrode of the second transistor is electrically connected to the first terminal of the driving circuit.
7 . The display substrate according to claim 6 , wherein, in at least two adjacent rows of pixel circuits included in the plurality of rows of pixel circuit,
first light emitting control lines electrically connected to the first transistor are electrically connected to each other; and/or, second light emitting control lines electrically connected to the second transistor are electrically connected to each other.
8 . The display substrate according to claim 1 , wherein the driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;
a first terminal of the first capacitor is electrically connected to the third node, and a second terminal of the first capacitor is electrically connected to the fourth node;
a first terminal of the second capacitor is electrically connected to the second node, and a second terminal of the second capacitor is electrically connected to the third node;
a gate electrode of the driving transistor is electrically connected to a control terminal of the driving circuit, a first electrode of the driving transistor is electrically connected to a first terminal of the driving circuit, and a second electrode of the driving transistor is electrically connected to a second terminal of the driving circuit.
9 . The display substrate according to claim 1 , wherein the first reset circuit includes a third transistor, and the second reset circuit includes a fourth transistor;
a gate electrode of the third transistor is electrically connected to the first reset line, a first electrode of the third transistor is electrically connected to the reference voltage terminal or the initial voltage terminal, and a second electrode of the third transistor is electrically connected to the third node;
a gate electrode of the fourth transistor is electrically connected to the first reset line, a first electrode of the fourth transistor is electrically connected to the reference voltage terminal or the power supply voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
10 . The display substrate according to claim 1 , wherein the first reset circuit includes a third transistor, and the second reset circuit includes a fourth transistor;
a gate electrode of the fourth transistor is electrically connected to the first reset line, a first electrode of the fourth transistor is electrically connected to the reference voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first node.
11 . The display substrate according to claim 1 , wherein the first reset circuit includes a third transistor, and the second reset circuit includes a fourth transistor;
a gate electrode of the third transistor is electrically connected to the first reset line, a first electrode of the third transistor is electrically connected to the reference voltage terminal, and a second electrode of the third transistor is electrically connected to the third node;
a gate electrode of the fourth transistor is electrically connected to the first reset line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first node.
12 . The display substrate according to claim 9 , wherein, in at least two adjacent rows of pixel circuits included in the plurality of rows of pixel circuit,
first reset lines electrically connected to the third transistor are electrically connected to each other; and/or, first reset lines electrically connected to the fourth transistor are electrically connected to each other.
13 . The display substrate according to claim 3 , wherein the data writing-in circuit includes a fifth transistor, and the third light emitting control circuit includes a sixth transistor;
a gate electrode of the fifth transistor is electrically connected to the scanning line, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the fourth node;
a gate electrode of the sixth transistor is electrically connected to the scanning line, a first electrode of the sixth transistor is electrically connected to the second node, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element;
the fifth transistor is an n-type transistor, and the sixth transistor is a p-type transistor; or, the fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor.
14 . The display substrate according to claim 4 , wherein the data writing-in circuit includes a fifth transistor, and the third light emitting control circuit includes a sixth transistor;
a gate electrode of the fifth transistor is electrically connected to the scanning line, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the fourth node;
a gate electrode of the sixth transistor is electrically connected to the third light emitting control line, a first electrode of the sixth transistor is electrically connected to the second node, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.
15 . The display substrate according to claim 5 , wherein the third reset circuit includes a seventh transistor;
a gate electrode of the seventh transistor is electrically connected to the second reset line, a first electrode of the seventh transistor is electrically connected to the initial voltage terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.
16 . A driving method, applied to the display substrate according to claim 1 , comprising: in at least two rows of pixel circuits included in the plurality of rows of pixel circuits,
controlling, by the first light emitting control circuit, the connection between the first node and the fourth node under the control of the first light emitting control signal provided by a same first light emitting control line; and/or,
controlling, by the second light emitting control circuit, the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the second light emitting control signal provided by a same second light emitting control line; and/or,
controlling, by the first reset circuit, the potential of the third node under the control of the first reset signal provided by a same first reset line.
17 . A display device, comprising the display substrate according to claim 1 .
18 . The display device according to claim 17 , further comprising a gate driving circuit, wherein the gate driving circuit comprises a plurality of stages of gate driving units;
the gate driving circuit is electrically connected to a control signal line, is configured to provide a control signal to the control signal line;
one stage of gate driving unit provides a control signal to at least one row of pixel circuits included in the display substrate.