Analog-to-digital converter metastability adjustment
A system for adjusting a metastability error in an analog-to-digital converter (ADC) can include a first metastability test circuit, which can be configured to determine whether a comparator can be in a first stage of the ADC has settled to a determinate binary state at a first time. The system can also include a second metastability test circuit, which can be configured to determine whether the comparator in the first stage of the ADC has settled to the determinate binary state at a second time, where the first time can be a first specified time period before the second time. The system can also include correction circuitry, which can be configured to adjust an output of the first stage when one or more of the first metastability test circuit or the second metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state.
1 . A system for adjusting a metastability error in an analog-to-digital converter (ADC), the system comprising:
a first metastability test circuit, configured to determine whether a comparator in a first stage of the ADC has settled to a determinate binary state at a first time;
a second metastability test circuit, configured to determine whether the comparator in the first stage of the ADC has settled to the determinate binary state at a second time, wherein the first time is a first specified time period before the second time; and
correction circuitry, configured to adjust an output of the first stage when at least one of the first metastability test circuit or the second metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state.
2 . The system of claim 1 , wherein the correction circuitry is configured to:
subtract a first metastability error correction value from the output of the first stage when the first metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state, wherein the first metastability error correction value represents a central tendency of the metastability error between the first time and the second time; and
subtract a second metastability error correction value from the output of the first stage when the second metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state, wherein the second metastability error correction value represents a central tendency of the metastability error between the second time and a third time.
3 . The system of claim 2 , wherein:
at least one of the first time or the second time are selected to increase a signal-to-noise ratio of an output of the ADC.
4 . The system of claim 3 , wherein:
the signal-to-noise ratio for two or more values of the at least one of the first time or the second time are determined using at least one of a computer model or a physical test circuit.
5 . The system of claim 2 , wherein the metastability error for a specified analog input value is calculated by:
recurrently:
applying the specified analog input value to an input of the ADC, wherein the ADC is configured to add a varying dither signal to an analog input and subtract the varying dither signal from a digital output; and
recording the digital output value and a sign value of the comparator; and
determining a central tendency of a product of the recorded digital output values and the corresponding sign values to determine the metastability error for the specified analog input value.
6 . The system of claim 5 , wherein:
the specified analog input value combined with the varying dither signal is uncorrelated to the sign value; and
the metastability error is correlated with the sign value.
7 . The system of claim 6 , wherein:
a product of the sign value and a sum of the specified analog input value and the varying dither signal averages to zero; and
a product of the metastability error and the sign value averages to an absolute value of the metastability error.
8 . The system of claim 7 , wherein the correction circuitry is configured to:
multiply the determined central tendency by the sign value to recover a sign of the metastability error.
9 . The system of claim 5 , wherein the determined metastability error represents an absolute value of the metastability error, wherein a sign value is assigned to the determined metastability error based on an output of the comparator in the first stage.
10 . The system of claim 1 , wherein at least one of the first metastability test circuit or the second metastability test circuit includes:
an exclusive or (XOR) gate, connected to both outputs of the comparator, wherein the XOR gate outputs a logical high value when the comparator has settled to the determinate binary state; and
a delay flip-flop, configured to capture the output value of the XOR gate based on an input clock signal.
11 . The system of claim 10 , wherein:
the first metastability test circuit and the second metastability test circuit share the XOR gate;
the first metastability test circuit includes a first delay flip-flop, configured to capture the output value of the XOR gate based on a first input clock signal;
the second metastability test circuit includes a second delay flip-flop, configured to capture the output value of the XOR gate based on a second input clock signal;
the first input clock signal is configured to trigger the first delay flip-flop to capture the output value of the XOR gate at the first time; and
the second input clock signal is configured to trigger the second delay flip-flop to capture the output value of the XOR gate at the second time.
12 . The system of claim 1 , comprising:
a third metastability test circuit, configured to determine whether the comparator in the first stage of the ADC has settled to the determinate binary state at a fifth time, wherein the fifth time is a second specified time period after the second time, wherein the correction circuitry is configured to adjust the output of the first stage when at least one of the first metastability test circuit, the second metastability test circuit, or the third metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state.
13 . The system of claim 1 , comprising:
a fourth metastability test circuit, configured to determine whether a comparator in a second stage of the ADC has settled to a determinate binary state at the first time;
a fifth metastability test circuit, configured to determine whether the comparator in the first stage of the ADC has settled to the determinate binary state at the second time; and
second correction circuitry, configured to adjust an output of the second stage when at least one of the fourth metastability test circuit or the fifth metastability test circuit determines that the comparator in the second stage has not settled to the determinate binary state.
14 . The system of claim 1 , wherein the ADC includes a pipelined ADC configuration.
15 . A method for adjusting a metastability error in an analog-to-digital converter (ADC), the method comprising:
determining whether a comparator in a first stage of the ADC has settled to a determinate binary state at a first time;
determining whether the comparator in the first stage of the ADC has settled to the determinate binary state at a second time, wherein the first time is a first specified time period before the second time; and
adjusting an output of the first stage when it is determined that the comparator in the first stage had not settled to the determinate binary state at at least one of the first time or the second time.
16 . The method of claim 15 , comprising:
subtracting a first metastability error correction value from the output of the first stage when it is determined that the comparator in the first stage had not settled to the determinate binary state at the first time, wherein the first metastability error correction value represents a central tendency of the metastability error between the first time and the second time; and
subtracting a second metastability error correction value from the output of the first stage when it is determined that the comparator in the first stage had not settled to the determinate binary state at the second time, wherein the second metastability error correction value represents a central tendency of the metastability error between the first time and a third time.
17 . The method of claim 16 , comprising:
selecting at least one of the first time or the second time to increase a signal-to-noise ratio of an output of the ADC.
18 . The method of claim 16 , comprising:
calculating the metastability error for a specified analog input value by:
recurrently:
applying the specified analog input value to an input of the ADC, wherein the ADC is configured to add a varying dither signal to an analog input and subtract the varying dither signal from a digital output; and
recording the digital output value and a sign value of the comparator; and
determining a central tendency of a product of the recorded digital output values and the corresponding sign values to determine the metastability error for the specified analog input value.
19 . The method of claim 18 , comprising;
multiplying the determined central tendency by the sign value to recover a sign of the metastability error.
20 . A method for determining a metastability error in an analog-to-digital converter (ADC), the method comprising:
calculating the metastability error for a specified analog input value by:
recurrently:
applying the specified analog input value to an input of the ADC, wherein the ADC is configured to add a varying dither signal to an analog input and subtract the varying dither signal from a digital output; and
recording the digital output value and a sign value of a comparator in a first stage of the ADC; and
determining a central tendency of a product of the recorded digital output values and the corresponding sign values to determine the metastability error for the specified analog input value.