Memory system that performs error correction using metric array and method of controlling the same
A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.
1 . A memory system comprising:
a non-volatile memory; and
a memory controller configured to:
encode data to be written into the non-volatile memory using an error-correction code that includes a Hamming code;
obtain a hard-read value of data read from the non-volatile memory using a read voltage;
obtain a plurality of soft-read values of data read from the non-volatile memory using a plurality of read voltages;
based on the hard-read value and the soft-read values, obtain a soft decision input data, each value of which indicates a likelihood that a corresponding bit of the read data is either 0 or 1;
obtain a hard decision data of the soft decision input data;
obtain a syndrome using the hard decision data and a parity check matrix of the error-correction code;
decoding the hard decision data using a predetermined decoding method to obtain decoded words that are different from each other;
obtain a plurality of metrics each of which indicates a distance between one of the decoded words and the soft decision input data;
generate a metric array using the obtained metrics; and
based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data, as a decoding result of the read data.
2 . The memory system according to claim 1 , wherein the memory controller is configured to:
with respect to each value of the metric array, subtract the smallest one of the metrics therefrom when the value of the metric array is different from the smallest one of the metrics, and subtract the second smallest one of the metrics therefrom when the value of the metric array is the same as the smallest one of the metrics, to obtain first values; and
obtain the soft decision output data based on the first values.
3 . The memory system according to claim 2 , wherein the memory controller is configured to:
multiply a sign of each value of the soft decision input data with a corresponding one of the first values, to obtain second values; and
obtain the soft decision output data based on the second values.
4 . The memory system according to claim 3 , wherein the memory controller is configured to:
with respect to each of the second values, subtract a corresponding one of values of the soft decision input data therefrom, to obtain third values; and
obtain the soft decision output data based on the third values.
5 . The memory system according to claim 4 , wherein the memory controller is configured to multiply a scale coefficient that is greater than 0 and equal to or smaller than 1 to each of the third values, to obtain the soft decision output data.
6 . The memory system according to claim 2 , wherein the memory controller is configured to:
perform the subtraction when the obtained syndrome is not 0; and
multiply a sign of each value of the soft decision input data with a predetermined constant to obtain the soft decision output data, when the obtained syndrome is 0.
7 . The memory system according to claim 1 , wherein the predetermined decoding method comprises bit flipping of at least one of bits of the hard decision data.
8 . The memory system according to claim 1 , wherein the predetermined decoding method comprises an Ordered Statistics Decoding (OSD) method.
9 . The memory system according to claim 1 , wherein the memory controller is configured to:
obtain the metric of a newly-obtained decoded word, and update the metric array, the smallest one of the metrics, and the second smallest one of the metrics, each time the newly-obtained decoded word is obtained.
10 . The memory system according to claim 9 , wherein the memory controller is configured to:
obtain a modified syndrome from the syndrome; and
obtain the metric of a newly-obtained decoded word using the modified syndrome.
11 . The memory system according to claim 9 , wherein the memory controller is configured to add an absolute value of one of values of the soft decision input data with 2 times an average value of absolute values of the values of the soft decision input data, to update a value of the metric array.
12 . The memory system according to claim 9 , wherein the memory controller is configured to add an absolute value of one of values of the soft decision input data with a predetermined constant, to update a value of the metric array.
13 . The memory system according to claim 9 , wherein the memory controller is configured to set a predetermined constant to update a value of the metric array.
14 . The memory system according to claim 1 , wherein the error-correction code comprises a Reed-Solomon (RS) code that comprises a combination of a single parity check code and the Hamming code.
15 . The memory system according to claim 1 , wherein the error-correction code comprises a concatenated code of a Reed-Solomon (RS) code and a first code different from the RS code, the RS code comprising a combination of a single parity check code and the Hamming code.
16 . The memory system according to claim 1 , wherein the metric array is a one-dimensional metric array.
17 . The memory system according to claim 1 , wherein the memory controller includes:
a first decoder configured to perform a hard-input hard-output (HIHO) decoding with respect to the data read from the non-volatile memory; and
a second decoder configured to perform a soft-input soft-output (SISO) decoding with respect to the data read from the non-volatile memory, to obtain the decoding result of the read data.
18 . The memory system according to claim 1 , wherein the second decoder is configured to perform the SISO decoding when the HIHO decoding of the data read from the non-volatile memory fails.
19 . A method of controlling a memory system including a non-volatile memory, the method comprising:
encoding data to be written into the non-volatile memory using an error-correction code that includes a Hamming code;
obtaining a hard-read value from data read from the non-volatile memory using a read voltage;
obtaining a plurality of soft-read values from data read the non-volatile memory using a plurality of read voltages;
based on the hard-read value and the soft-read values, obtaining a soft decision input data, each value of which indicates a likelihood that a corresponding bit of the read data is either 0 or 1;
obtaining a hard decision data of the soft decision input data;
obtaining a syndrome using the hard decision data and a parity check matrix of the error-correction code;
decoding the hard decision data using a predetermined decoding method to obtain decoded words that are different from each other;
obtaining a plurality of metrics each of which indicates a distance between one of the decoded words and the soft decision input data;
generating a metric array using the obtained metrics; and
based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtaining a soft decision output data corresponding to the soft decision input data.