Single patterning cylindrical transistor and capacitor dynamic random access memory
Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.
1 . A memory device, comprising:
a plurality of vertically aligned transistors, each of the transistors comprising an annular semiconductor structure coupled to an independent bit line,
the transistors comprising a shared word line extending vertically through each of the annular semiconductor structures, wherein the word line comprises a first portion adjacent a first of the annular semiconductor structures, a second portion adjacent a second of the annular semiconductor structures, and a third portion between the first and second portions, wherein the third portion has a lateral width less than a lateral width of the first portion and less than a lateral width of the second portion; and
a plurality of vertically aligned capacitors, each of the capacitors comprising an annular first capacitor plate surrounding an annular capacitor dielectric structure, wherein each of the annular first capacitor plates are in contact with one of the annular semiconductor structures,
the capacitors comprising a shared second capacitor plate extending vertically through each of the annular capacitor dielectric structures and the surrounding annular first capacitor plates.
2 . The memory device of claim 1 , wherein the second capacitor plate comprises a first portion adjacent a first of the annular first capacitor plates, a second portion adjacent a second of the annular first capacitor plates, and a third portion between the first and second portions, wherein the third portion has a lateral width less than a lateral width of the first portion and less than a lateral width of the second portion.
3 . The memory device of claim 1 , wherein a first of the annular semiconductor structures comprises a first portion forming an outer ring of the first annular semiconductor structure and a second portion extending from the first portion into an interior of the first annular semiconductor structure.
4 . The memory device of claim 1 , wherein a first of the annular first capacitor plates comprises a first portion forming an outer ring of the first annular first capacitor plate and a second portion extending from the first portion into an interior of the first capacitor plate.
5 . The memory device of claim 1 , wherein each of the transistors further comprises an annular gate dielectric structure between the annular semiconductor structure and the word line.
6 . The memory device of claim 5 , further comprising gate dielectric material on both of and extending between a first of the annular gate dielectric structures and a second of the annular gate dielectric structures.
7 . The memory device of claim 1 , wherein a centerline extending laterally through a center of the second capacitor plate and through a center of the word line is substantially orthogonal to a line defined by a length of a first of the independent bit lines.
8 . The memory device of claim 1 , wherein an angle between a line defined by a length of a first of the independent bit lines and a centerline extending laterally through a center of the second capacitor plate and through a center of the word line is between 50° and 70°.
9 . The memory device of claim 8 , wherein the line is at a second angle of between 25° and 35° with respect to an edge of an integrated circuit die comprising the vertically aligned transistors, the independent bit lines, and the vertically aligned capacitors.
10 . The memory device of claim 1 , wherein the annular semiconductor structures have a first lateral width, and the annular first capacitor plates have a second lateral width not more than 1.5 times the first lateral width.
11 . The memory device of claim 10 , further comprising:
a cooling structure operable to remove heat from an IC die comprising the annular semiconductor structures to achieve an operating temperature at or below −25° C.
12 . The memory device of claim 1 , wherein the annular capacitor dielectric structures comprise one of titanium and oxygen, tantalum and oxygen, zirconium and oxygen, aluminum and oxygen, hafnium and oxygen, silicon and oxygen, silicon and carbon, gallium and nitrogen, strontium, titanium, and oxygen, barium, titanium, and oxygen, or barium, strontium, titanium, and oxygen.
13 . A system, comprising:
an integrated circuit (IC) die comprising a one transistor-one capacitor dynamic random access memory (1T-TC DRAM) device, comprising:
a plurality of transistors each comprising an annular semiconductor structure coupled to a bit line,
the transistors comprising a word line extending through each of the annular semiconductor structures, wherein the word line comprises a first portion adjacent a first of the annular semiconductor structures, a second portion adjacent a second of the annular semiconductor structures, and a third portion between the first and second portions, wherein the third portion has a lateral width less than a lateral width of the first portion and less than a lateral width of the second portion; and
a plurality of capacitors, each of the capacitors comprising an annular first capacitor plate surrounding an annular capacitor dielectric, wherein each of the annular first capacitor plates are in contact with a respective one of the annular semiconductor structures,
the capacitors comprising a second capacitor plate extending through each of the annular capacitor dielectrics and the surrounding annular first capacitor plates; and
a power supply coupled to the IC die.
14 . The system of claim 13 , wherein a first of the annular semiconductor structures comprises a first portion forming an outer ring of the first annular semiconductor structure and a second portion extending from the first portion into an interior of the first annular semiconductor structure.
15 . The system of claim 13 , wherein an angle between a line defined by a length of a first of the bit lines and a centerline extending laterally through a center of the second capacitor plate and through a center of the word line is not less than 100°.
16 . The system of claim 15 , wherein the line is at a second angle of not more than 80° with respect to an edge of the IC die.
17 . A memory device, comprising:
a plurality of transistors each comprising an annular semiconductor structure coupled to a bit line, the transistors comprising a word line extending through each of the annular semiconductor structures, wherein the word line comprises a first portion adjacent a first of the annular semiconductor structures, a second portion adjacent a second of the annular semiconductor structures, and a third portion between the first and second portions, wherein the third portion has a lateral width less than a lateral width of the first portion and less than a lateral width of the second portion; and
a plurality of capacitors, each of the capacitors comprising an annular first capacitor plate surrounding an annular capacitor dielectric, wherein each of the annular first capacitor plates are in contact with a respective one of the annular semiconductor structures,
the capacitors comprising a second capacitor plate extending through each of the annular capacitor dielectrics and the surrounding annular first capacitor plates.
18 . The memory device of claim 17 , wherein the second capacitor plate comprises a first portion adjacent a first of the annular first capacitor plates, a second portion adjacent a second of the annular first capacitor plates, and a third portion between the first and second portions, wherein the third portion has a lateral width less than a lateral width of the first portion and less than a lateral width of the second portion.
19 . The memory device of claim 17 , wherein a first of the annular semiconductor structures comprises a first portion forming an outer ring of the first annular semiconductor structure and a second portion extending from the first portion into an interior of the first annular semiconductor structure.
20 . The memory device of claim 17 , wherein a first of the annular first capacitor plates comprises a first portion forming an outer ring of the first annular first capacitor plate and a second portion extending from the first portion into an interior of the first capacitor plate.
21 . The memory device of claim 17 , wherein each of the transistors further comprises an annular gate dielectric structure between the annular semiconductor structure and the word line.
22 . The memory device of claim 17 , wherein a centerline extending laterally through a center of the second capacitor plate and through a center of the word line is substantially orthogonal to a line defined by a length of a first of the bit lines.
23 . The memory device of claim 17 , further comprising:
an integrated circuit (IC) die comprising the transistors and the capacitors; and
a power supply coupled to the IC die.