Nanosheet transistors with buried power rails
A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.
1 . A semiconductor structure comprising:
a substrate;
a first field effect transistor (FET) formed on the substrate and comprising a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions;
a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls;
a first FET shared contact electrically interconnected with the buried power rail and the first FET second source-drain region;
a bottom dielectric isolation located between and electrically isolating the substrate and the first FET first and second source-drain regions;
a first FET electrically isolating region directly adjacent and separating the bottom dielectric isolation and the buried power rail sidewalls, and separating the buried power rail from the substrate, the first FET electrically isolating region including a first FET shallow trench isolation liner in direct contact with the substrate and the bottom dielectric isolation;
a contact etch-stop liner extending around the first FET first source-drain region except for a section of the first FET first source-drain region that is in contact with the first FET shared contact; and
an inter-layer dielectric located directly adjacent to the first FET first and second source-drain regions, the first FET shared contact, and the contact etch-stop liner, wherein the contact etch-stop liner is, at least partially, sandwiched between the inter-layer dielectric and the first FET electrically isolating region.
2 . The semiconductor structure of claim 1 , further comprising a second field effect transistor (FET), adjacent the first field effect transistor, and formed on the substrate and comprising a second FET first source-drain region, a second FET second source-drain region, a second FET gate between the second FET first and second source-drain regions, and a second FET channel region adjacent the second FET gate and between the second FET first and second source-drain regions;
wherein the buried power rail is located between the adjacent first and second field effect transistors.
3 . The semiconductor structure of claim 2 , wherein the electrically isolating region comprises an electrically insulating dielectric compound.
4 . The semiconductor structure of claim 2 , wherein the electrically isolating region comprises an encapsulated gap.
5 . The semiconductor structure of claim 4 , wherein the gap comprises an air gap.
6 . The semiconductor structure of claim 2 , wherein:
the first field effect transistor channel region comprises a first field effect transistor nanosheet channel region;
the second field effect transistor channel region comprises a second field effect transistor nanosheet channel region;
the first field effect transistor gate comprises a first field effect transistor all-around gate; and
the second field effect transistor gate comprises a second field effect transistor all-around gate.
7 . A semiconductor array structure comprising:
a substrate;
a plurality of field effect transistors formed on the substrate, each comprising a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region adjacent the gate and between the first and second source-drain regions, the plurality of field effect transistors being arranged in lateral rows;
a plurality of buried power rails, buried in the substrate, each having a top at a level lower than the channel regions, each having buried power rail sidewalls;
a plurality of shared contacts electrically interconnected with the buried power rails and the second source-drain regions;
bottom dielectric isolation located between and electrically isolating the substrate and the first and second source-drain regions of the plurality of field effect transistors;
electrically isolating regions directly adjacent and separating the bottom dielectric isolation and the buried power rail sidewalls of each of the plurality of buried power rails, and separating the buried power rails from the substrate, the electrically isolating regions including a shallow trench isolation liner in direct contact with the substrate and the bottom dielectric isolation; and
an inter-layer dielectric located directly adjacent to the first and second source-drain regions of the plurality of field effect transistors, the plurality of shared contacts, and a contact etch-stop liner sandwiched between the inter-layer dielectric the electrically isolating regions,
wherein the buried power rails are located between adjacent rows of the field effect transistors; and
wherein first adjacent pairs of the lateral rows are n-type and second adjacent pairs of the lateral rows are p-type.
8 . The semiconductor array structure of claim 7 , wherein the electrically isolating regions comprise an electrically insulating dielectric compound.
9 . The semiconductor array structure of claim 7 , wherein the electrically isolating regions comprise encapsulated gaps.
10 . The semiconductor array structure of claim 9 , wherein the gaps comprises air gaps.
11 . The semiconductor array structure of claim 7 , wherein:
the channel regions comprise nanosheet channel regions; and
the gates comprise all-around gates.
12 . The semiconductor array structure of claim 7 , further comprising the contact etch-stop liner extending around the first source-drain regions except for sections of the first source-drain regions that are in contact with the shared contacts.