Semiconductor structures and method for manufacturing a semiconductor structure
The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.
1 . A semiconductor structure comprising:
a backside redistribution layer (RDL);
a plurality of bumps disposed on a first surface of the backside RDL;
a dielectric layer disposed on a second surface of the backside RDL;
a plurality of through dielectric vias (TDVs) passing through the dielectric layer;
a plurality of first dies disposed within the dielectric layer, wherein each of the first dies comprises:
a first substrate disposed on the backside RDL;
a plurality of through silicon vias (TSVs) passing through the first substrate and contacting conductive paths in the backside RDL;
a first device layer disposed on the first substrate;
a first RDL disposed on the first device layer;
a computation circuit formed in the first device layer and the first RDL; and
a second die stacked on the plurality of first dies in a face-to-face manner, wherein the second die comprises:
a second substrate;
a second device layer disposed on the second substrate;
a second RDL disposed on the second device layer, wherein the second RDL is coupled to the first RDL and the plurality of TDVs; and
a memory circuit formed in the second device layer and the second RDL;
wherein:
each of the computation circuit is configured to transmit signals to the memory circuit through the first RDL and the second RDL;
each of the plurality of first dies is configured to receive a first supply voltage through at least one first bump of the plurality of bumps, at least one first conductive path in the backside RDL, and at least one TSV of the plurality of TSVs; and
the second die is configured to receive a second supply voltage through at least one second bump of the plurality of bumps, at least one second conductive path in the backside RDL, and at least one TDV of the plurality of TDVs.
2 . The semiconductor structure of claim 1 , wherein an input/output circuit is further formed in the second device layer and the second RDL.
3 . The semiconductor structure of claim 2 , wherein the computation circuit is configured to transmit signals to the input/output circuit through the first RDL and the second RDL, and the input/output circuit is configured to transmit signals to an external circuit through at least one bump of the plurality of bumps and at least one TDV of the plurality of TDVs.
4 . The semiconductor structure of claim 1 , wherein the memory circuit comprises a static random-access memory (SRAM), a resistive random-access memory (RRAM), or a magnetoresistive random-access memory (MRAM).
5 . The semiconductor structure of claim 1 , wherein the second die comprises a plurality of input/output circuits, and each of the plurality of first dies comprises a computation circuit coupled to an input/output circuit of the plurality of input/output circuits.
6 . The semiconductor structure of claim 1 , wherein the first substrate is thinner than the second substrate.
7 . The semiconductor structure of claim 1 , wherein a die size of the second die is greater than a die size of each of the plurality of first dies.
8 . A semiconductor chiplet comprising:
an interposer;
the semiconductor structure of claim 1 disposed on the interposer; and
a plurality of high bandwidth memories (HBM) disposed on the interposer.
9 . A semiconductor structure comprising:
a backside redistribution layer (RDL);
a plurality of bumps disposed on a first surface of the backside RDL;
a dielectric layer disposed on a second surface of the backside RDL;
a plurality of through dielectric vias (TDVs) passing through the dielectric layer;
a plurality of first dies disposed within the dielectric layer, wherein each of the first dies comprises:
a first substrate disposed on the backside RDL;
a plurality of through silicon vias (TSVs) passing through the first substrate and contacting conductive paths in the backside RDL;
a first device layer disposed on the first substrate;
a first RDL disposed on the first device layer;
a computation circuit formed in the first device layer and the first RDL; and
a second die stacked on the plurality of first dies in a face-to-face manner, wherein the second die comprises:
a second substrate;
a second device layer disposed on the second substrate;
a second RDL disposed on the second device layer, wherein the second RDL is coupled to the first RDL and the plurality of TDVs; and
a memory circuit formed in the second device layer and the second RDL;
wherein:
each of the computation circuit is configured to transmit signals to the memory circuit through the first RDL and the second RDL; and
power supply lines for providing power supply to the plurality of first dies and the second die are disposed in regions other than a region between the plurality of first dies and the second die where the plurality of first dies and the second die overlap when viewed from top.
10 . The semiconductor structure of claim 9 , wherein:
each of the plurality of first dies is configured to receive a first supply voltage through at least one first bump of the plurality of bumps, at least one first conductive path in the backside RDL, and at least one TSV of the plurality of TSVs; and
the second die is configured to receive a second supply voltage through at least one second bump of the plurality of bumps, at least one second conductive path in the backside RDL, and at least one TDV of the plurality of TDVs.
11 . The semiconductor structure of claim 9 , wherein an input/output circuit is further formed in the second device layer and the second RDL.
12 . The semiconductor structure of claim 11 , wherein the computation circuit is configured to transmit signals to the input/output circuit through the first RDL and the second RDL, and the input/output circuit is configured to transmit signals to an external circuit through at least one bump of the plurality of bumps and at least one TDV of the plurality of TDVs.
13 . The semiconductor structure of claim 9 , wherein the memory circuit comprises a static random-access memory (SRAM), a resistive random-access memory (RRAM), or a magnetoresistive random-access memory (MRAM).
14 . The semiconductor structure of claim 9 , wherein the second die comprises a plurality of input/output circuits, and each of the plurality of first dies comprises a computation circuit coupled to an input/output circuit of the plurality of input/output circuits.
15 . The semiconductor structure of claim 9 , wherein the first substrate is thinner than the second substrate.
16 . The semiconductor structure of claim 9 , wherein a die size of the second die is greater than a die size of each of the plurality of first dies.