IP Library › Granted Patent US 12,656,849
Granted Patent B2
US 12,656,849 · App. 18/606,381 · Granted Jun 16, 2026

Performance and power tuning user interface

Inventors: Alexander S. Duenas (Markham, CA); Omer Irshad (Markham, CA); Sishanthy Balachandran (Markham, CA); Arpit Nitinbhai Patel (Markham, CA); Andrew Savio D'Souza (Markham, CA); Oleksandr Khodorkovsky (Markham, CA)
Assignee: ATI Technologies ULC
G06F1/3231G06F1/28G06F9/451G06F3/0484
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Quick Facts
Patent No.
US 12,656,849
App. No.
18/606,381
Granted
Jun 16, 2026
Kind
B2
Abstract

Power management in a computing device. A driver is registered with an operating system (OS) executing on the computing device to receive information about a position of a user interface control. If the user interface control is moved, the driver receives a notification of the user interface control position and determines a power management intervention based on the position The driver transmits the power management intervention to power control circuitry which sets a power setting of the computing device based on the intervention.

Claims (33)

1 . A method for power management in a computing device, the method comprising:

receiving, by an operating system (OS) executing on the computing device, a first notification; and

transmitting, by the OS, to power control circuitry, a second notification indicating a power management intervention based on the first notification, wherein the power management intervention includes at least one of:

setting a maximum voltage or maximum power of the computing device;

setting a maximum voltage or maximum power for a specific power domain of the computing device;

setting a maximum clock frequency or maximum power of the computing device; or

setting a maximum clock frequency for a specific clock domain of the computing device.

2 . The method of claim 1 , wherein the first notification indicates a position of a user interface control.

3 . The method of claim 1 , wherein the OS receives the first notification on a periodic basis.

4 . The method of claim 1 , wherein the computing device comprises a central processing unit (CPU).

5 . The method of claim 1 , wherein the power control circuitry comprises a system management unit (SMU).

6 . The method of claim 1 , wherein the power control circuitry is implemented on a central processing unit (CPU).

7 . The method of claim 1 , wherein the power management intervention includes the setting of the maximum clock frequency or the maximum power of the computing device.

8 . The method of claim 1 , wherein the power management intervention includes the setting of the maximum clock frequency for the specific clock domain of the computing device.

9 . The method of claim 1 , wherein the power management intervention is determined based at least in part on whether the computing device is operating on battery power or on an external power supply.

10 . A computing device configured for power management, comprising:

circuitry configured to:

receive, by an operating system (OS) executing on the computing device, a first notification; and

transmit, by the OS, to power control circuitry, a second notification indicating a power management intervention based on the first notification wherein the power management intervention includes at least one of:

setting a maximum voltage or maximum power of the computing device;

setting a maximum voltage or maximum power for a specific power domain of the computing device;

setting a maximum clock frequency or maximum power of the computing device; or

setting a maximum clock frequency for a specific clock domain of the computing device.

11 . The computing device of claim 10 , wherein the first notification indicates a position of a user interface control.

12 . The computing device of claim 10 , wherein the OS receives the first notification of on a periodic basis.

13 . The computing device of claim 10 , wherein the computing device comprises a central processing unit (CPU).

14 . The computing device of claim 10 , wherein the power control circuitry comprises a system management unit (SMU).

15 . The computing device of claim 10 , wherein the power control circuitry is implemented on a central processing unit (CPU).

16 . The computing device of claim 10 , wherein the power management intervention includes the setting of the maximum voltage or the maximum power of the computing device.

17 . The computing device of claim 10 , wherein the power management intervention includes the setting of the maximum voltage or the maximum power for the specific power domain of the computing device.

18 . The computing device of claim 10 , wherein the power management intervention includes the setting of the maximum clock frequency or the maximum power of the computing device.

19 . The computing device of claim 10 , wherein the power management intervention includes the setting of the maximum clock frequency for the specific clock domain of the computing device.

20 . The computing device of claim 10 , further comprising a discrete graphics processing unit (GPU), wherein the power control circuitry is configured to adjust a maximum power limit for the discrete GPU based on the power management intervention indicated by the second notification.

Continuity (3)
Continuation 17486175 · Sep 27, 2021
Continuation 16213828 · Dec 7, 2018
Related Publication 20240219991A1 · Jul 4, 2024
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