Granted Patent B2

US 12,657,005 · App. 17/799,977 · Granted Jun 16, 2026

Inventors: Takeshi Aoki (Ebina, JP); Yoshiyuki Kurokawa (Sagamihara, JP); Munehiro Kozuma (Atsugi, JP); Takuro Kanemura (Sapporo, JP)

Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

G06F7/5443G06F17/16G06G7/16G06N3/048G06N3/065H10D30/6755

Abstract

Claims (58)

1 . A semiconductor device comprising a first circuit and a second circuit,

wherein the second circuit comprises a first switch, a second switch, a current/voltage converter circuit, and a first transistor,

wherein the first circuit is electrically connected to a first terminal of the first switch,

wherein a second terminal of the first switch is electrically connected to a first terminal of the current/voltage converter circuit,

wherein a second terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor,

wherein a second terminal of the first transistor is electrically connected to a first terminal of the second switch,

wherein the first circuit is configured to:

retain W 1 to W m as a plurality of pieces of first data; and

make a current responsive to a value of

∑

i

=

1

m

⁢

W

i

⁢

X

i

flow to a first terminal of the second circuit when X 1 to X m are input to the first circuit as a plurality of pieces of second data,

wherein the current/voltage converter circuit is configured to output, from the second terminal of the current/voltage converter circuit, a first potential responsive to the current input to the first terminal of the current/voltage converter circuit,

wherein the first transistor is configured to:

output the first potential from the second terminal of the first transistor when the first potential is higher than or equal to a sum of a potential of a gate of the first transistor and a threshold voltage of the first transistor; and

output a potential having the sum from the second terminal of the first transistor when the first potential is lower than the sum, and

wherein m is an integer greater than or equal to 1.

2 . The semiconductor device according to claim 1 ,

wherein the current/voltage converter circuit comprises an operational amplifier and a load,

wherein an inverting input terminal of the operational amplifier is electrically connected to the first terminal of the current/voltage converter circuit and a first terminal of the load, and

wherein an output terminal of the operational amplifier is electrically connected to a second terminal of the load.

3 . The semiconductor device according to claim 2 ,

wherein the load comprises any one of a resistor, a diode, and a transistor.

4 . The semiconductor device according to claim 1 , further comprising:

a third circuit,

wherein the third circuit comprises a current mirror circuit,

wherein the first circuit comprises a first cell, a second cell, a first wiring, a second wiring, and a third wiring,

wherein the first cell comprises a first capacitor,

wherein the second cell comprises a second capacitor,

wherein the first wiring is electrically connected to the first cell, the first terminal of the second circuit, and the third circuit,

wherein the second wiring is electrically connected to the second cell and the third circuit,

wherein the third wiring is electrically connected to a first terminal of the first capacitor and a first terminal of the second capacitor,

wherein the first cell is configured to:

retain a first potential in a second terminal of the first capacitor; and

make a current in an amount responsive to the first potential flow to the first wiring,

wherein the second cell is configured to:

retain a second potential in a second terminal of the second capacitor; and

make a current in an amount responsive to the second potential flow to the second wiring,

wherein the current mirror circuit is configured to make a current in the same amount as the current flowing to the second wiring flow to the first wiring,

wherein one of the plurality of pieces of first data is data responsive to a potential difference between the first potential and the second potential, and

wherein a potential responsive to one of the plurality of pieces of second data is input to the third wiring.

5 . The semiconductor device according to claim 1 ,

wherein the first cell comprises a second transistor and a third transistor,

wherein the second cell comprises a fourth transistor and a fifth transistor, wherein a first terminal of the second transistor is electrically connected to the second terminal of the first capacitor and a gate of the third transistor,

wherein a first terminal of the third transistor is electrically connected to the first wiring,

wherein a first terminal of the fourth transistor is electrically connected to the second terminal of the second capacitor and a gate of the fifth transistor, and

wherein a first terminal of the fifth transistor is electrically connected to the second wiring.

6 . An electronic device comprising the semiconductor device according to claim 1 and a housing,

wherein the semiconductor device performs a product-sum operation and an arithmetic operation of a ReLU function.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (48)