Accelerator capable of executing fast dynamic change in acceleration type
An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.
1 . An accelerator package apparatus, comprising:
an interface to plug into an electronic system;
a field programmable gate array integrated circuit to perform acceleration;
a general purpose processor integrated circuit to execute software related to the acceleration; and
controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator package's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.
2 . The accelerator package of claim 1 wherein the controller circuitry is to dynamically change, without rebooting the general purpose processor integrated circuit, the field programmable gate array integrated circuit's acceleration and the software executed by the general purpose processor that is related to the field programmable gate array integrated circuit's acceleration.
3 . The accelerator package of claim 2 wherein the accelerator package further comprises:
a first non-volatile storage space to store different images for respective types of acceleration that the field programmable gate array integrated circuit is able to perform, the different images including power information that describes different power consumption of the field programmable gate array integrated circuit when performing the respective types of acceleration.
4 . The accelerator package of claim 3 wherein the different images further comprise respective bitstreams to configure the field programmable gate array integrated circuit with respective logic to perform the respective types of acceleration.
5 . The accelerator package of claim 3 wherein the controller is to determine one or more power settings for the general purpose processor integrated circuit in view of the power information and the accelerator package's power budget.
6 . The accelerator package of claim 2 wherein the controller is to change the software because of the change in the field programmable gate array integrated circuit's acceleration.
7 . The accelerator package of claim 2 wherein the change in acceleration is from one of the following to another, different one of the following:
network acceleration;
virtual radio access network (vRAN) acceleration;
open virtual switching (OVS) acceleration;
memory offloading acceleration; or
software function call dispatching.
8 . The accelerator package of claim 1 wherein the dynamic change is in response to a command received by the accelerator package.
9 . The accelerator package of claim 1 wherein the controller is further to keep the accelerator package's power consumption within a power budget that is assigned to the accelerator package.
10 . The accelerator package of claim 9 wherein, in order to keep the accelerator package's power consumption within the power budget, the controller is to cause power to be provided to the field programmable gate array integrated circuit consistent with configuration specific power profile information for the field programmable gate array integrated circuit, and, provide at least a portion of remaining power in the budget to the general purpose processor integrated circuit.
11 . The accelerator package of claim 1 wherein the controller is to request an external power management entity to rebalance its power allocations.
12 . The accelerator package of claim 1 wherein the accelerator package further comprises:
a current detect circuit;
respective power throttling and/or power management circuits within the field programmable gate array integrated circuit and the general purpose processor integrated circuit to perform power throttling and/or power management of the field programmable gate array integrated circuit and the general purpose processor; and
telemetry and power management circuits within the controller to command the power throttling and/or power management circuits to lower the power of the field programmable gate array integrated circuit and the general purpose processor integrated circuit in response to a signal from the current detect circuit that the accelerator package has exceeded a power level.
13 . A computing system, comprising:
a plurality of processors;
a memory coupled to the plurality of processors;
a peripheral controller; and
an accelerator package plugged into an interface of the computing system, the accelerator package to include:
a field programmable gate array integrated circuit to perform acceleration;
a general purpose processor integrated circuit to execute software related to the acceleration; and
controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator package's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.
14 . The computing system of claim 13 wherein the controller circuitry is to dynamically change, without rebooting the general purpose processor integrated circuit, the field programmable gate array integrated circuit's acceleration and the software executed by the general purpose processor that is related to the field programmable gate array integrated circuit's acceleration.
15 . The computing system of claim 14 wherein the accelerator package further comprises:
a first non-volatile storage space to store different images for respective types of acceleration that the field programmable gate array integrated circuit is able to perform, the different images including power information that describes different power consumption of the field programmable gate array integrated circuit when performing the respective types of acceleration.
16 . The computing system of claim 15 wherein the different images further comprise respective bitstreams to configure the field programmable gate array integrated circuit with respective logic to perform the respective types of acceleration.
17 . The computing system of claim 15 wherein the controller is to determine one or more power settings for the general purpose processor integrated circuit in view of the power information and the accelerator package's power budget.
18 . The computing system of claim 14 wherein the controller is to change the software because of a change from a first type of acceleration to a second type of acceleration.
19 . The computing system of claim 18 wherein one of the first and second types of acceleration are any of the following:
network acceleration;
virtual radio access network (vRAN) acceleration;
open virtual switching (OVS) acceleration;
memory offloading acceleration; or
software function call dispatching.
20 . The computing system of claim 13 wherein the accelerator package is one of:
a) a Peripheral Connect Interconnect express (PCIe) adaptor card; or
b) an Open Compute Project Accelerator module (OAM).
21 . A data center, comprising:
racks of computers, wherein, one of the computers includes an accelerator package, the accelerator package including:
a field programmable gate array integrated circuit to perform acceleration; acceleration,
a general purpose processor integrated circuit to execute software related to the acceleration; and
controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, a balance of power between the field programmable gate array integrated circuit and the general purpose processor integrated circuit;
data center power and/or service control software executing on CPU resources of one or more other computers of the data center, the data center power and/or service control software to command the accelerator package to perform the dynamic change; and
a network coupled between the racks of computers and the one or more other computers.
22 . The data center of claim 21 wherein the controller is to also change the software as part of the dynamic change because of a change from a first type of acceleration to a second type of acceleration.
23 . The data center of claim 22 wherein one of the first and second types of acceleration are one of the following:
network acceleration;
virtual radio access network (vRAN) acceleration;
open virtual switching (OVS) acceleration;
memory offloading acceleration; or
software function call dispatching.
24 . The data center of claim 21 wherein the accelerator package is one of:
a) a Peripheral Connect Interconnect express (PCIe) adaptor card; or
b) an Open Compute Project Accelerator module (OAM).
25 . The data center of claim 21 wherein the controller circuit is to perform at least one of the following:
modulate performance and power of memory disposed on the accelerator package; or
modulate performance and power of at least one of the field programmable gate array integrated circuit and the general purpose integrated circuit based on a temperature.