IP Library › Granted Patent US 12,657,151
Granted Patent B2
US 12,657,151 · App. 18/659,773 · Granted Jun 16, 2026

PCIe device

Inventors: Yong Tae Jeon (Icheon, KR); Byung Cheol Kang (Icheon, KR); Seung Duk Cho (Icheon, KR); Sang Hyun Yoon (Icheon, KR); Se Hyeon Han (Icheon, KR); Jae Young Jang (Icheon, KR)
Assignee: SK hynix Inc.
G06F13/4221G06F1/08G06F7/588G06F13/4045
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Quick Facts
Patent No.
US 12,657,151
App. No.
18/659,773
Granted
Jun 16, 2026
Kind
B2
Abstract

A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Claims (29)

1 . A peripheral component interconnect express (PCIe) device, comprising:

a physical function performing operations associated with a Peripheral Component Interconnect Express (PCIe) interface according to a physical function (PF) type;

a common function performing the operations according to the physical function type or a virtual function (VF) type; and

a function type controller changing a function type of the common function into the virtual function type or the physical function type based on function type setting information,

wherein the function type setting information includes function type mapping information indicating a mapping relationship between the common function and the function type of the common function.

2 . The PCIe device of claim 1 , wherein each of the physical function and the second common function comprises:

a configuration space including registers for configuring each of the physical function and the common function to perform the operations.

3 . The PCIe device of claim 2 , wherein the function type controller changes the function type of the common function by changing values of the registers included in the configuration space of the common function based on the function type setting information.

4 . The PCIe device of claim 2 , wherein the function type controller, based on pointer values indicating capabilities to be enabled among values of the registers, enables capabilities associated with the function type determined for each of the physical function and the common function.

5 . The PCIe device of claim 2 , wherein the function type controller changes the function type of the common function as being one of the physical function type, the virtual function type, and a disable function type in which the operations are disabled.

6 . The PCIe device of claim 5 , wherein the function type controller disables the registers included in the configuration space of the common function when the common function is changed to be the disable function type.

7 . The PCIe device of claim 1 , wherein the common function determined as the physical function type performs the operations based on a base address register (BAR) included in a configuration space of the common function.

8 . The PCIe device of claim 7 , wherein the common function determined as the physical function type performs the operations based on registers corresponding to the operations included in the configuration space of the common function.

9 . The PCIe device of claim 1 , wherein the common function determined as the virtual function type is associated with the physical function, and performs the operations based on a base address register included in a configuration space of the physical function.

10 . The PCIe device of claim 9 , wherein the physical function is a single root I/O virtualization (SR-IOV) capability enabled function, and

wherein the common function is enabled according to a virtual function (VF) enable value included in a SR-IOV capability register of the physical function.

11 . The PCIe device of claim 9 , wherein the common function performs the operations based on registers corresponding to the operations included in the configuration space of the physical function.

12 . The PCIe device of claim 9 , wherein the common function performs a reset operation on the common function in response to at least one of a reset request for the physical function, a reset request for the common function, and a clear operation of the VF enable value of the physical function.

13 . The PCIe device of claim 1 , wherein the operations include at least one of a data processing operation of receiving a command, an error handling operation of detecting an error and reporting the error, and a power management operation of managing power of a function.

14 . The PCIe device of claim 1 , wherein each of the physical function and the common function comprises:

an operation controller controlling each of the physical function and the common function to perform the operations according to the function type determined for each of the physical function and the common function.

15 . The PCIe device of claim 2 , wherein the function type controller, based on pointer values indicating capabilities to be enabled among values of the registers, disables capabilities not associated with the function type determined for each of the physical function and the common function, and performs clock gating on registers of the capabilities disabled among the registers.

16 . The PCIe device of claim 5 , wherein the function type controller performs clock gating on the registers when the common function is changed to be the disable function type.

17 . The PCIe device of claim 7 , wherein the common function performs a reset operation on the common function in response to a reset request for the common function provided.

18 . The PCIe device of claim 1 , wherein the physical function includes a base address register included in a configuration space of the physical function,

wherein the common function determined as the virtual function type is associated with the physical function, and performs the operations based on the base address register included in the configuration space of the physical function.

19 . The PCIe device of claim 1 , wherein the PCIe device receives the function type setting information from the host.

20 . The PCIe device of claim 1 , wherein each of the physical function and the common function corresponds to an independent operation unit for providing physical resources of the PCIe device.

21 . The PCIe device of claim 1 , wherein PCIe device completion information is provided to a host in accordance with the changing of the function type of the common function.

Priority Claims (3)
KR 10-2021-0048063 · Apr 13, 2021 · national
KR 10-2021-0048073 · Apr 13, 2021 · national
KR 10-2021-0048077 · Apr 13, 2021 · national
Continuity (3)
Continuation 18406919 · Jan 8, 2024
Continuation 17506610 · Oct 20, 2021
Related Publication 20240289295A1 · Aug 29, 2024
References Cited (56)
US 6647434B1 · Kamepalli · 2003 [cited by applicant]
US 7979592B1 · Pettey et al. · 2011 [cited by applicant]
US 8503468B2 · Akyol et al. · 2013 [cited by applicant]
US 10007545B2 · Graham · 2018 [cited by examiner]
US 10635499B2 · Huynh · 2020 [cited by applicant]
US 20060195617A1 · Arndt et al. · 2006 [cited by applicant]
US 20080147943A1 · Freimuth · 2008 [cited by examiner]
US 20100115174A1 · Akyol et al. · 2010 [cited by applicant]
US 20110106981A1 · Watkins et al. · 2011 [cited by applicant]
US 20120131232A1 · Brownlow · 2012 [cited by examiner]
US 20130339955A1 · Prawer et al. · 2013 [cited by applicant]
US 20170277573A1 · Huynh · 2017 [cited by applicant]
US 20180239737A1 · Cha et al. · 2018 [cited by applicant]
US 20180367518A1 · Singh et al. · 2018 [cited by applicant]
US 20190042350A1 · Nadathur et al. · 2019 [cited by applicant]
US 20190042741A1 · Abodunrin et al. · 2019 [cited by applicant]
US 20200004703A1 · Sankaran et al. · 2020 [cited by applicant]
US 20200012530A1 · Kakaiya et al. · 2020 [cited by applicant]
US 20200042246A1 · Maharana et al. · 2020 [cited by applicant]
US 20200278935A1 · Borikar et al. · 2020 [cited by applicant]
US 20200409732A1 · Kovacevic · 2020 [cited by applicant]
US 20210089466A1 · Shanbhogue et al. · 2021 [cited by applicant]
US 20210200703A1 · Simionescu et al. · 2021 [cited by applicant]
US 20210247935A1 · Beygi et al. · 2021 [cited by applicant]
US 20220188073A1 · Bowman et al. · 2022 [cited by applicant]
US 20220300442A1 · Jeon et al. · 2022 [cited by applicant]
US 20220300448A1 · Jeon · 2022 [cited by applicant]
US 20220327080A1 · Jeon et al. · 2022 [cited by applicant]
US 20220327081A1 · Jeon et al. · 2022 [cited by applicant]
US 20220327082A1 · Jeon et al. · 2022 [cited by applicant]
US 20220327228A1 · Jeon et al. · 2022 [cited by applicant]
CN 106663069A · 2017 [cited by applicant]
CN 108028813A · 2018 [cited by applicant]
CN 110287660A · 2019 [cited by applicant]
CN 111092773A · 2020 [cited by applicant]
CN 112422492A · 2021 [cited by applicant]
CN 112565043A · 2021 [cited by applicant]
JP 2010016819A · 2010 [cited by applicant]
KR 2010016819A · 2010 [cited by applicant]
KR 1020130034036A · 2013 [cited by applicant]
KR 101704776B1 · 2017 [cited by applicant]
KR 1020170013713A · 2017 [cited by applicant]
KR 1020170051475A · 2017 [cited by applicant]
KR 1020170057237A · 2017 [cited by applicant]
KR 1020210024195A · 2021 [cited by applicant]
Office Action dated Jul. 30, 2024 for the U.S. Appl. No. 18/406,919. [cited by applicant]
Jose Fernando Zazo et al., “A PCIe OMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances,” IFEE, Dec. 7, 2015. [cited by applicant]
“PCI Express® Base Specification Revision 4.0 Version 1.0”, PCI Express, Sep. 27, 2017. [cited by applicant]
Office Action dated Mar. 30, 2023 for U.S. Appl. No. 17/504,351. [cited by applicant]
Office Action dated Mar. 2, 2023 for U.S. Appl. No. 17/504,884. [cited by applicant]
PCIe Express, PCI Express Base Specification 3.0, Nov. 10, 2010, pp. 1-4, 97-122 (Year: 2010). [cited by applicant]
Final Office Action dated Sep. 14, 2023 for U.S. Appl. No. 17/504,351. [cited by applicant]
Office Action dated Jan. 18, 2024 for the U.S. Appl. No. 17/504,346. [cited by applicant]
Notice of Allowance dated Mar. 7, 2024 for U.S. Appl. No. 17/504,351. [cited by applicant]
“Virtual Function Number Assignment”, An IP.com Prior Art Database Technical Disclosure, Jul. 11, 2008, URL:https://priorart.ip.com/IPCOM/000172526. [cited by applicant]
Notice of Office Action for Taiwanese Patent Application No. 111113693, dated Aug. 29, 2025. [cited by applicant]