Granted Patent B2

US 12,657,300 · App. 18/896,018 · Granted Jun 16, 2026

Inventors: Chankyu Han (Suwon-si, KR); Jihyuk Lim (Suwon-si, KR); Chiyang Hwang (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

G06F21/566G06F12/023G06F2221/034

Abstract

Claims (79)

1 . An electronic device supporting multiple domains, the electronic device comprising:

memory storing one or more computer programs; and

one or more processors communicatively coupled to the memory and operable in a first domain and a second domain and comprising processing circuitry,

wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to:

detect a shared memory use request by the first domain or the second domain,

allocate shared memory for communication between multiple domains comprising the first domain and the second domain based on a memory area designated in the memory, based on the shared memory use request,

register a tag for the shared memory in a first memory area of the first domain and a second memory area of the second domain, and

detect a memory safety bug for the shared memory shared between the first domain and the second domain, based on the tag.

2 . The electronic device of claim 1 ,

wherein the multiple domains comprise a non-secure world domain and a secure world domain, and

wherein the non-secure world domain and the secure world domain comprise one or more domains.

3 . The electronic device of claim 1 , wherein the one or more computer programs further include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to detect a memory safety bug for the shared memory by using memory tagging extension (MTE) capable of detecting a memory safety bug through hardware.

4 . The electronic device of claim 1 ,

wherein each of the multiple domains comprises a software layer and a hardware layer,

wherein the hardware layer is shared for the multiple domains, and

wherein the software layer is divided by the multiple domains and comprises an application layer, an operating system layer, a virtualization layer, and a monitor layer.

5 . The electronic device of claim 4 ,

wherein the virtualization layer is configured to operate in a privileged mode allowing performing of limited operations of the shared memory, and

wherein the virtualization layer comprises a controller monitoring and detecting a memory safety bug that invade between the multiple domains.

6 . The electronic device of claim 5 , wherein the one or more computer programs further include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to process operations to request, register, manage, and/or deny the shared memory.

7 . The electronic device of claim 5 , wherein the controller comprises:

an interface checking memory requests, permissions, and tag information;

a manager processing requests transmitted through the interface; and

a tag agent detecting a memory safety bug for the shared memory.

8 . The electronic device of claim 7 , wherein the tag agent is configured to manage a table based on an identification number of a domain requesting allocation of a memory area for shared memory, a memory address, a memory size, a tag requested for allocation to the shared memory, and/or a conversion address.

9 . The electronic device of claim 7 , wherein the one or more computer programs further include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to:

receive a shared memory allocation request from the first domain of the multiple domains,

manage a table for address conversion and allocate tags for shared memory through address conversion in the table,

configure a shared memory tag in the shared memory based on tag information related to the allocated tag,

transmit the shared memory allocation request to the second domain of the multiple domains,

receive a commit message from the second domain,

determine whether the memory area requested for allocation in the first domain matches the memory area requested for allocation in the second domain,

complete final registration for the shared memory when the memory areas requested for allocation match each other, and

transmit a registration completion response for the shared memory having an identical shared memory tag in the first domain and the second domain to the first domain and the second domain.

10 . The electronic device of claim 9 , wherein a memory area having an identical tag in the shared memory is registered by the first domain and the second domain.

11 . The electronic device of claim 9 , wherein the one or more computer programs further include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to:

detect a memory safety bug for each of the multiple domains based on the registered tag, and

deny access to the memory area by the corresponding domain due to tag mismatch when a memory safety bug is detected.

12 . The electronic device of claim 1 , further comprising a hardware including:

a first processor configured to store executable instructions and be programmable to execute the instructions, and

a second processor configured to manage memory allocation and deallocation for each of the multiple domains,

wherein the first processor and the second processor are shared between multiple domains.

13 . The electronic device of claim 12 , wherein the memory comprises dynamic memory used in the operation of the first processor.

14 . A method of operating an electronic device supporting multiple domains, the method comprising:

detecting a shared memory use request by a first domain or a second domain;

allocating shared memory for communication between multiple domains comprising the first domain and the second domain based on a memory area designated in the memory, based on the shared memory use request;

registering a tag for the shared memory in a first memory area of the first domain and a second memory area of the second domain; and

detecting a memory safety bug for the shared memory shared between the first domain and the second domain, based on the tag.

15 . The method of claim 14 ,

wherein the multiple domains comprise a non-secure world domain and a secure world domain, and

wherein the non-secure world domain and the secure world domain comprise one or more domains.

16 . The method of claim 14 , further comprising:

detecting a memory safety bug for the shared memory by using memory tagging extension (MTE) capable of detecting a memory safety bug through hardware.

17 . The method of claim 14 ,

wherein each of the multiple domains comprises a software layer and a hardware layer,

wherein the hardware layer is shared for the multiple domains,

wherein the software layer is divided by the multiple domains and comprises an application layer, an operating system layer, a virtualization layer, and a monitor layer,

wherein the virtualization layer is configured to operate in a privileged mode allowing performing of limited operations of the shared memory,

wherein the virtualization layer comprises a controller monitoring and detecting a memory safety bug that invade between the multiple domains, and

further comprising:

performing, by the controller, operations of requesting, registering, managing, and/or denying the shared memory.

18 . The method of claim 17 , further comprising:

receiving a shared memory allocation request from the first domain of the multiple domains;

managing a table for address conversion and allocating tags for shared memory through address conversion in the table;

configuring a shared memory tag in the shared memory based on tag information related to the allocated tag;

transmitting the shared memory allocation request to the second domain of the multiple domains;

receiving a commit message from the second domain;

determining whether the memory area requested for allocation in the first domain matches the memory area requested for allocation in the second domain;

completing final registration for the shared memory when the memory areas requested for allocation match each other; and

transmitting a registration completion response for the shared memory having an identical shared memory tag in the first domain and the second domain to the first domain and the second domain.

19 . The method of claim 18 , further comprising:

registering a memory area having an identical tag in the shared memory by the first domain and the second domain,

detecting a memory safety bug for each of the multiple domains based on the registered tag, and

denying access to the memory area by the corresponding domain due to tag mismatch when a memory safety bug is detected.

20 . One or more non-transitory computer-readable storage media storing computer-executable instructions that, when executed by one or more processors of an electronic device individually or collectively, cause the one or more processors to perform operations, the operations comprising:

detecting a shared memory use request by a first domain or a second domain;

allocating shared memory for communication between multiple domains comprising the first domain and the second domain based on a memory area designated in the memory, based on the shared memory use request;

registering a tag for the shared memory in a first memory area of the first domain and a second memory area of the second domain; and

detecting a memory safety bug for the shared memory shared between the first domain and the second domain, based on the tag.

Assignments (1)

Priority Claims (2)

Continuity (2)

References Cited (21)