Synaptic device, neuromorphic device including synaptic device, and operating methods thereof
View Patent ↗A synaptic device, a neuromorphic device including the synaptic device, and operating methods thereof are disclosed. A synaptic device may comprise a channel, a charge trap layer directly contacting the channel, a blocking insulating layer disposed on the charge trap layer, a control electrode disposed on the blocking insulating layer, a first terminal connected to a first region of the channel, and a second terminal connected to a second region of the channel. The synaptic device may change a post-synaptic current (PSC) and control synaptic plasticity according to a control signal applied to the control electrode. The synaptic device may have a SONS (doped poly-silicon/blocking oxide/charge trap nitride/silicon channel) structure. The synaptic device may have SADP characteristics, SDDP characteristics, SFDP characteristics, SNDP characteristics, and STDP characteristics.
1 . A synaptic device comprising:
a channel;
a charge trap layer directly contacting the channel;
a blocking insulating layer disposed on the charge trap layer;
a control electrode disposed on the blocking insulating layer;
a first terminal connected to a first region of the channel; and
a second terminal connected to a second region of the channel;
wherein the synaptic device is configured to change a post-synaptic current (PSC) and control synaptic plasticity according to a control signal applied to the control electrode.
2 . The synaptic device of claim 1 , wherein the control electrode is a gate electrode, the first terminal is a source, the second terminal is a drain, and
wherein the PSC is a current flowing between the source and the drain, and the control signal is a gate voltage.
3 . The synaptic device of claim 2 , wherein the synaptic device has a SONS structure.
4 . The synaptic device of claim 2 , wherein the gate electrode includes silicon, the blocking insulating layer includes an oxide, the charge trap layer includes a nitride, and the channel includes silicon.
5 . The synaptic device of claim 2 , wherein the synaptic device has a characteristic that charges trapped in the charge trap layer in response to application of the gate voltage are diffused and outflowed to the channel over time.
6 . The synaptic device of claim 2 , wherein the synaptic device controls the synaptic plasticity according to one or more of an amplitude, a duration, a frequency, a number, and a timing of a pulse of the gate voltage.
7 . The synaptic device of claim 1 , wherein the synaptic device has a spike amplitude dependent plasticity (SADP) characteristic, a spike duration dependent plasticity (SDDP) characteristic, a spike frequency dependent plasticity (SFDP) characteristic, a spike number dependent plasticity (SNDP) characteristic, and a spike timing dependent plasticity (STDP) characteristic.
8 . The synaptic device of claim 1 , wherein the synaptic device has a paired-pulse facilitation (PPF) characteristic.
9 . A neuromorphic device comprising the synaptic device according to claim 1 .
10 . The neuromorphic device of claim 9 , further comprising a CMOS peripheral circuit connected to the synaptic device.
11 . The neuromorphic device of claim 10 , wherein the control electrode is a gate electrode, the first terminal is a source, the second terminal is a drain, and
wherein the PSC is a current flowing between the source and the drain, and the control signal is a gate voltage.
12 . The neuromorphic device of claim 11 , wherein the CMOS peripheral circuit includes:
a pre-synaptic neuron circuit configured to apply a pre-spike signal to the gate electrode of the synaptic device; and
a post-synaptic neuron circuit configured to receive the PSC through the source of the synaptic device.
13 . A method of operating a synaptic device, the method comprising:
applying a control signal to a control electrode of the synaptic device to control a post-synaptic current (PSC) and synaptic plasticity of the synaptic device; and
outputting the PSC to generate a post-spike signal,
wherein the synaptic device includes a channel, a charge trap layer directly contacting the channel, a blocking insulating layer disposed on the charge trap layer, the control electrode disposed on the blocking insulating layer, a first terminal connected to a first region of the channel, and a second terminal connected to a second region of the channel.
14 . The method of claim 13 , wherein the control electrode is a gate electrode, the first terminal is a source, the second terminal is a drain, and
wherein the PSC is a current flowing between the source and the drain, and the control signal is a gate voltage.
15 . The method of claim 14 , wherein the synaptic device has a SONS structure.
16 . The method of claim 14 , wherein the gate electrode includes silicon, the blocking insulating layer includes an oxide, the charge trap layer includes a nitride, and the channel includes silicon.
17 . The method of claim 14 , wherein the synaptic device has a characteristic that charges trapped in the charge trap layer in response to the application of the gate voltage are diffused and outflowed to the channel over time.
18 . The method of claim 14 , wherein the synaptic plasticity is controlled according to one or more of a amplitude, a duration, a frequency, a number, and a timing of a pulse of the gate voltage.
19 . The method claim 13 , wherein the synaptic device has a spike amplitude dependent plasticity (SADP) characteristic, a spike duration dependent plasticity (SDDP) characteristic, a spike frequency dependent plasticity (SFDP) characteristic, a spike number dependent plasticity (SNDP) characteristic, and a spike timing dependent plasticity (STDP) characteristic.
20 . The method of claim 13 , wherein the synaptic device has a paired-pulse facilitation (PPF) characteristic.