Memory device and memory controller configured to perform re-training based on temperature information and electronic device including the same
An electronic device includes a system on-chip that outputs a write clock and a write data signal, and a memory device that receives the write data signal based on the write clock and outputs a read data signal and a data strobe signal whose frequency is different from a frequency of the write clock. The memory device further includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs a first training in initialization of the electronic device and performs a second training in an operation after the initialization. The memory device performs a counting operation during an operation of an interval oscillator in the second training and corrects a final count value with reference to temperature information of the memory device.
1 . An electronic device comprising:
a system on-chip configured to output a write clock and a write data signal; and
a memory device configured to receive the write data signal based on the write clock and to output a read data signal and a data strobe signal whose timing is different from a timing of the write clock,
wherein the memory device includes:
a first interval oscillator configured to replicate a difference between a path of the write clock and a path of the read data signal; and
a second interval oscillator configured to replicate a difference between the path of the write clock and a path of the write data signal,
wherein the system on-chip is configured to:
obtain a first delay time according to the difference between the path of the write clock and the path of the read data signal; and
obtain a second delay time according to the difference between the path of the write clock and the path of the write data signal, and
wherein the memory device is configured to:
obtain a first counting value while the first interval oscillator operates, the first counting value being indicative of the first delay time;
obtain a second counting value while the second interval oscillator operates, the second counting value being indicative of the second delay time;
correct the first counting value depending on a range in which a temperature of the memory device belongs to obtain a corrected first counting value; and
correct the second counting value depending on the range in which the temperature belongs to obtain a corrected second counting value.
2 . The electronic device of claim 1 , wherein, in initialization of the memory device, the system on-chip performs first training such that a delay of the write clock is adjusted based on the first delay time or such that a delay of the write data signal is adjusted based on the second delay time, and
wherein, in an operation of the memory device, the system on-chip performs second training such that the delay of the write clock is adjusted based on a third delay time corresponding to the corrected first counting value or such that the delay of the write data signal is adjusted based on a fourth delay time corresponding to the corrected second counting value.
3 . The electronic device of claim 1 , wherein the memory device is configured to:
obtain the first delay time in response to a FIFO (First In First Out) read command received from the system on-chip; and
obtain the second delay time in response to a FIFO write command received from the system on-chip.
4 . The electronic device of claim 1 , wherein the memory device is configured to obtain at least one of the first counting value and the second counting value in a time period between an interval oscillator start command and an interval oscillator stop command received from the system on-chip.
5 . The electronic device of claim 1 , wherein the memory device includes:
a first counter configured to output the first counting value;
a second counter configured to output the second counting value;
a temperature sensor configured to obtain information about the temperature of the memory device;
a control logic circuit configured to obtain the corrected first counting value by correcting the first counting value based on the information about the temperature and to obtain the corrected second counting value by correcting the second counting value based on the information about the temperature; and
a mode register configured to store the corrected first counting value and the corrected second counting value.
6 . The electronic device of claim 5 , wherein the memory device is configured to output the corrected first counting value and the corrected second counting value in response to a mode register read command received from the system on-chip.
7 . The electronic device of claim 5 , wherein the system on-chip includes:
a read data strobe signal receiver configured to receive a read data strobe signal;
a first delay circuit configured to control a delay of the read data strobe signal output from the read data strobe signal receiver based on the first counting value;
a second delay circuit configured to control a delay of the write data signal based on the second counting value; and
a data transmitter configured to transmit the write data signal output from the second delay circuit.
8 . The electronic device of claim 1 , wherein the first interval oscillator includes a first plurality of inverters, and the second interval oscillator includes a second plurality of inverters,
wherein the number of the first plurality of inverters is different from the number of the second plurality of inverters.
9 . The electronic device of claim 2 , wherein, when the second training is performed, the adjustment of the delay of the write clock based on the third delay time and the adjustment of the delay of the write data signal based on the fourth delay time are performed at different times.
10 . The electronic device of claim 1 , wherein the system on-chip and the memory device operate based on an LPDDR (Low Power Double Data Rate) standard.