Shared power footer circuit
A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.
1 . A device, comprising:
a first power rail for a first power domain;
a second power rail for a second power domain, wherein the second power rail is different from the first power rail;
a first circuit block connected to the first power rail;
a second circuit block connected to the second power rail;
a virtual VSS terminal, wherein the first and second circuit blocks are both connected to the virtual VSS terminal;
a ground terminal;
a footer circuit connected between the virtual VSS terminal and the ground terminal;
a first footer circuit configured to receive a first footer control signal in the first power domain; and
a second footer circuit configured to receive a second footer control signal in the second power domain.
2 . The device of claim 1 , wherein at least one of the first and second footer circuits is configured to control a connection of the virtual VSS terminal from the ground terminal in response to the first and second footer control signals, respectively.
3 . The device of claim 1 , wherein the virtual VSS terminal includes first and second virtual VSS terminals, wherein the first footer control signal controls a connection between the first virtual VSS terminal and the ground terminal, and wherein the second footer control signal controls a connection between the second virtual VSS terminal and the ground terminal.
4 . The device of claim 1 , wherein the first footer circuit includes a first footer circuit transistor and the second footer circuit includes a second footer circuit transistor, and wherein a connection of the virtual VSS terminal to the ground terminal is controlled by at least one of the first and second footer circuit transistors.
5 . The device of claim 1 , further comprising:
a third power rail for a third power domain; and
a third circuit block connected between the third power rail and the virtual VSS terminal.
6 . The device of claim 5 , further comprising:
a third footer circuit connected between the virtual VSS terminal and the ground terminal, the third footer circuit configured to receive a third footer control signal driven by the third power domain.
7 . The device of claim 5 , wherein the virtual VSS terminal includes first and second virtual VSS terminals, wherein the first footer control signal controls a connection between the first virtual VSS terminal and the ground terminal, wherein the second footer control signal controls a connection between the second virtual VSS terminal and the ground terminal, and wherein the first and third circuit blocks are both connected to the first virtual VSS terminal, and wherein the second circuit block is connected to the second virtual VSS terminal.
8 . The device of claim 1 , further comprising:
a fourth circuit block connected between the first power rail and the virtual VSS terminal.
9 . The device of claim 8 , further comprising:
a fourth footer circuit connected between the virtual VSS terminal and the ground terminal, the fourth footer circuit configured to receive a fourth footer control signal driven by the second power domain.
10 . A memory device, comprising:
a first power rail for a first power domain;
a second power rail for a second power domain, and wherein the second power domain is different from the first power domain;
a memory array connected to the first power rail;
a first peripheral circuit connected to the second power rail;
a virtual VSS terminal, wherein the first peripheral circuit and the memory array are both connected to the virtual VSS terminal;
a ground terminal;
a footer circuit connected between the virtual VSS terminal and the ground terminal;
a first footer circuit configured to receive a first footer control signal; and
a second footer circuit configured to receive a second footer control signal.
11 . The device of claim 10 , wherein at least one of the first footer control signal and the second footer control signal is generated based on a predetermined power mode.
12 . The device of claim 11 , wherein the predetermined power mode includes at least one of a normal operation mode, a deep sleep mode, a sleep mode and a shutdown mode;
wherein the virtual VSS terminal includes a first virtual VSS terminal connected to the memory array, and a second virtual VSS terminal connected to the first peripheral circuit;
wherein in the normal operation mode, the first and second virtual VSS terminals are both connected to the ground terminal;
wherein in the sleep mode, the first virtual VSS terminal is connected to the ground terminal and the second virtual VSS terminal is disconnected to the ground terminal; and
wherein in the deep sleep mode or the shutdown mode, the first and second virtual VSS terminals are both disconnected to the ground terminal.
13 . The device of claim 10 , further comprising a second peripheral circuit connected to a third power rail having a third power domain, and the third power domain being the lowest power domain among the first, second and third power domains.
14 . The device of claim 13 , wherein each of the first and second peripheral circuits includes at least one of a local I/O circuit, a local controller, a global I/O circuit, and a global controller.
15 . The device of claim 14 , wherein the first peripheral circuit includes at least one of the local controller and the global controller, and wherein the second peripheral circuit includes at least one of the local I/O circuit and the global I/O circuit.
16 . A method for operating a device, comprising:
providing a first circuit block connected between a first virtual VSS terminal and a first power rail to operate in a first power domain;
providing a second circuit block connected between a second virtual VSS terminal and a second power rail to operate in a second power domain, wherein the second power rail is different from the first power rail, and wherein the second power domain is different from the first power domain;
placing the first circuit block in a predetermined power mode by controlling a connection between the first virtual VSS terminal and a ground terminal in response to a first footer control signal; and
placing the second circuit block in the predetermined power mode by controlling a connection between the second virtual VSS terminal and the ground terminal in response to a second footer control signal;
wherein the first footer control signal is driven by the first power domain, and wherein the second footer control signal is driven by the second power domain.
17 . The method of claim 16 , wherein the predetermined power mode includes at least one of a normal operation mode, a deep sleep mode, a sleep mode and a shutdown mode, and wherein at least one of the modes is configured to maintain power to one of the first or second power domains and disconnecting power to the other.
18 . The method of claim 16 , wherein controlling the connection between the first virtual VSS terminal and the ground terminal includes applying the first footer control signal to a first footer circuit connected between the first virtual VSS terminal and the ground terminal, and wherein controlling the connection between the second virtual VSS terminal and the ground terminal includes applying the second footer control signal to a second footer circuit connected between the second virtual VSS terminal and the ground terminal.
19 . The method of claim 16 , wherein the first and second footer control signals are respectively driven by the first and second power domains includes applying the first and second power domains to respective gates of first and second foot control circuit.
20 . The method of claim 16 , wherein the first circuit block is a memory array, and wherein the second circuit block is a peripheral circuit.