IP Library Granted Patent US 12,658,263
Granted Patent B2
US 12,658,263 · App. 18/320,409 · Granted Jun 16, 2026

Storage devices with region-dependent initial program voltages

Inventors: Seunghan Lee (Suwon-si, KR); Bumjun Kim (Suwon-si, KR); Bodon Jeong (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G11C16/12G11C16/0433G11C16/30
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Quick Facts
Patent No.
US 12,658,263
App. No.
18/320,409
Granted
Jun 16, 2026
Kind
B2
Abstract

A memory device of a storage device includes a memory cell array divided into a plurality of regions including a first region and a second region. The device controller is configured to control the storage device so as to allow the memory device to program first data into the first region using a first initial program voltage, and to program second data into the second region using a second initial program voltage having a different magnitude from the first initial program voltage.

Claims (58)

1 . A storage device comprising:

a memory device comprising a memory cell array comprising a plurality of memory cells and divided into a plurality of regions comprising a first region and a second region; and

a device controller configured to control the storage device such that the memory device programs first data into the first region using a first initial program voltage, and programs second data into the second region using a second initial program voltage having a different magnitude from the first initial program voltage,

wherein the memory cell array has a vertical structure comprising a substrate,

wherein the second region is located farther from the substrate than the first region is from the substrate,

wherein the second region comprises a memory cell farthest from the substrate among the plurality of memory cells, and the first region comprises a memory cell closest to the substrate among the plurality of memory cells, and

wherein the first initial program voltage is higher in magnitude than the second initial program voltage.

2 . The storage device of claim 1 , wherein the first region has a longer program time than the second region.

3 . The storage device of claim 1 , further comprising a power management device configured to supply the first initial program voltage through a voltage supply line, and

wherein the memory device comprises:

a voltage divider configured to divide the first initial program voltage supplied from the voltage supply line and output the second initial program voltage, and

a switching circuit configured to output selectively one of the first initial program voltage and the second initial program voltage.

4 . The storage device of claim 3 , wherein the device controller is further configured to output a first control signal when the first data is to be programmed into the first region, and output a second control signal when the second data is to be programmed into the second region, and

wherein the switching circuit is further configured to output the first initial program voltage in response to the first control signal, and output the second initial program voltage in response to the second control signal.

5 . The storage device of claim 1 , further comprising:

a power management device configured to supply the first initial program voltage through a voltage supply line;

a voltage divider configured to divide the first initial program voltage supplied from the voltage supply line and output the second initial program voltage; and

a switching circuit configured to output selectively one of the first initial program voltage and the second initial program voltage to the memory device.

6 . The storage device of claim 1 , further comprising:

a power management device configured to supply the first initial program voltage through a first voltage supply line, and supply the second initial program voltage through a second voltage supply line; and

a switching circuit configured to output selectively one of the first initial program voltage and the second initial program voltage to the memory device.

7 . The storage device of claim 6 , wherein the device controller is further configured to output a first control signal when the first data is to be programmed into the first region, and output a second control signal when the second data is to be programmed into the second region, and

wherein the switching circuit is further configured to output the first initial program voltage in response to the first control signal, and output the second initial program voltage in response to the second control signal.

8 . The storage device of claim 1 , further comprising a capacitor configured to store charges;

a voltage generating circuit configured to generate the first initial program voltage based on the charges stored in the capacitor, and supply the first initial program voltage through a first voltage supply line;

a power management device configured to supply the second initial program voltage through a second voltage supply line; and

a switching circuit configured to output selectively one of the first initial program voltage and the second initial program voltage to the memory device.

9 . The storage device of claim 1 , wherein the plurality of regions is divided based on program time of respective memory cells in the plurality of regions.

10 . A storage device comprising:

a power management device configured to supply a first initial program voltage;

a device controller configured to output a control signal;

a voltage divider configured to divide the first initial program voltage to generate one or more second initial program voltages;

a switching circuit configured to select, in response to the control signal, a selected initial program voltage from among a plurality of initial program voltages comprising the first initial program voltage and the one or more second initial program voltages; and

a memory cell array comprising a plurality of memory cells and configured to program data using the selected initial program voltage that is selected by the switching circuit,

wherein the memory cell array has a vertical structure comprising a substrate,

wherein the memory cell array is divided into a plurality of regions, the plurality of regions comprising a first region and a second region, the second region being located farther from the substrate than the first region is from the substrate,

wherein the second region comprises a memory cell farthest from the substrate among the plurality of memory cells, and the first region comprises a memory cell closest to the substrate among the plurality of memory cells, and

wherein the first initial program voltage corresponds to the first region, and the second initial program voltage corresponds to the second region, the first initial program voltage being higher in magnitude than the second initial program voltage.

11 . The storage device of claim 10 , wherein the device controller is further configured to output the control signal such that the switching circuit selects the selected initial program voltage based on a correspondence between the selected initial program voltage and a region into which the data is to be programmed.

12 . The storage device of claim 11 , wherein the second region has a shorter program time than the first region.

13 . The storage device of claim 10 , wherein the plurality of regions is divided based on program time of respective memory cells in the plurality of regions.

14 . A storage device comprising:

a plurality of voltage supply lines configured to transfer respectively a plurality of initial program voltages comprising a first initial program voltage and a second initial program voltage that have different magnitudes;

a device controller configured to output a control signal;

a switching circuit configured to select a selected initial program voltage from among the plurality of initial program voltages transferred through the plurality of voltage supply lines in response to the control signal; and

a memory cell array comprising a plurality of memory cells and configured to program data using the initial program voltage selected by the switching circuit,

wherein the memory cell array has a vertical structure comprising a substrate,

wherein the memory cell array is divided into a plurality of regions, the plurality of regions comprising a first region and a second region, the second region being located farther from the substrate than the first region is from the substrate,

wherein the second region comprises a memory cell farthest from the substrate among the plurality of memory cells, and the first region comprises a memory cell closest to the substrate among the plurality of memory cells, and

wherein the first initial program voltage corresponds to the first region, and the second initial program voltage corresponds to the second region, the first initial program voltage being higher in magnitude than the second initial program voltage.

15 . The storage device of claim 14 , further comprising a power management device configured to supply the plurality of initial program voltages through the plurality of voltage supply lines.

16 . The storage device of claim 14 , further comprising:

a capacitor configured to store charges;

a voltage generating circuit configured to generate the first initial program voltage based on the charges stored in the capacitor, and supply the first initial program voltage through a first voltage supply line among the plurality of voltage supply lines; and

a power management device configured to supply the second initial program voltage through a second voltage supply line among the plurality of voltage supply lines.

17 . The storage device of claim 14 , wherein the device controller is further configured to output the control signal such that the switching circuit selects the selected initial program voltage that corresponds to a region into which the data is to be programmed.

18 . The storage device of claim 17 , wherein the second region has a shorter program time than the first region.

19 . The storage device of claim 14 , wherein the plurality of regions is divided based on program time of memory cells in the respective plurality of regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2023
From: LEE, SEUNGHAN; KIM, BUMJUN; JEONG, BODON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 063700/0293 →
Priority Claims (1)
KR 10-2022-0141512 · Oct 28, 2022 · national
Continuity (1)
Related Publication 20240145012A1 · May 2, 2024
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