High precision on-chip RC oscillator
Methods, systems, and computer products are presented herein for generating a clock signal using an on-chip ultra-low power (ULP) RC oscillator. An on-chip ultra-low power (ULP) RC oscillator comprises a first comparator, a second comparator, and a flip flop. The first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit. Each of the first bias voltage and the second bias voltage directly varies with a thermal voltage. A flip-flop is electrically coupled to the first comparator and the second comparator. The flip-flop is configured to generate a clock signal based on the first and the second comparator output signals.
1 . An on-chip ultra-low power (ULP) RC oscillator, the on-chip ULP RC oscillator comprising:
a first comparator, wherein the first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit, the first bias voltage generation circuit being configured to generate a first bias voltage, and the first capacitor circuit being configured to generate a first proportional to absolute temperature (PTAT) voltage, wherein the first comparator is configured to compare the first bias voltage and the first PTAT voltage, and to generate a first comparator output signal based on the comparison;
a second comparator, wherein the second comparator comprises a first input electrically coupled to a second bias voltage generation circuit and a second input electrically coupled to a second capacitor circuit, the second bias voltage generation circuit being configured to generate a second bias voltage, and the second capacitor circuit being configured to generate a second PTAT voltage, wherein the second comparator is configured to compare the second bias voltage and the second PTAT voltage and to generate a second comparator output signal based on the comparison, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage; and
a flip-flop electrically coupled to the first comparator and the second comparator, wherein:
the flip-flop is configured to generate a clock signal based on the first and the second comparator output signals,
the flip-flop is an RS flip-flop,
the flip-flop is electrically coupled to the first comparator and the second comparator,
a first input of the flip-flop is configured to receive the first comparator output signal,
a second input of the flip-flop is configured to receive the second comparator output signal,
a first output of the flip-flop is configured to provide a first offset correction to the first comparator, and
a second output of the flip-flop is configured to provide a second offset correction to the second comparator.
2 . The on-chip ULP RC oscillator of claim 1 , wherein the first and the second bias voltage generation circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series with a resistor, wherein the PTAT current source is configured to produce a current and provide the current to the resistor.
3 . The on-chip ULP RC oscillator of claim 2 , wherein the PTAT current source is biased sub-threshold.
4 . The on-chip ULP RC oscillator of claim 2 , wherein the PTAT current source is configured to produce a current that is proportional to the thermal voltage.
5 . The on-chip ULP RC oscillator of claim 2 , wherein the resistor comprises a poly-resistor, and wherein the resistor is characterized by a bias resistance, R B .
6 . The on-chip ULP RC oscillator of claim 1 , wherein the first and the second capacitor circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series to an NMOS transistor, a capacitor, and a temperature compensation circuit, and wherein the PTAT current source is configured to produce a current and provide the current to the NMOS transistor and the capacitor.
7 . The on-chip ULP RC oscillator of claim 6 , wherein the PTAT current source is biased sub-threshold.
8 . The on-chip ULP RC oscillator of claim 6 , wherein the PTAT current source is configured to produce a current that is proportional to the thermal voltage.
9 . The on-chip ULP RC oscillator of claim 6 , wherein the NMOS transistor is electrically coupled at its source to the capacitor, and the NMOS transistor is electrically coupled at its gate to the flip-flop.
10 . The on-chip ULP RC oscillator of claim 6 , wherein the capacitor is a Metal-Insulator-Metal (MIM) capacitor.
11 . The on-chip ULP RC oscillator of claim 1 , wherein the thermal voltage varies with an operating temperature of the on-chip ULP RC oscillator.
12 . The on-chip ULP RC oscillator of claim 1 , wherein the RS flip-flop is electrically coupled to the first capacitor circuit and the second capacitor circuit, wherein the first output of the RS flip-flop is configured to drive the second capacitor circuit, and wherein the second output of the RS flip-flop is configured to drive the first capacitor circuit.
13 . An on-chip ULP RC oscillator, the on-chip ULP RC oscillator comprising:
a first comparator, wherein the first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit, the first bias voltage generation circuit being configured to generate a first bias voltage, and the first capacitor circuit being configured to generate a first proportional to absolute temperature (PTAT) voltage, wherein the first comparator is configured to compare the first bias voltage and the first PTAT voltage, and to generate a first comparator output signal based on the comparison;
a second comparator, wherein the second comparator comprises a first input electrically coupled to a second bias voltage generation circuit and a second input electrically coupled to a second capacitor circuit, the second bias voltage generation circuit being configured to generate a second bias voltage, and the second capacitor circuit being configured to generate a second PTAT voltage, wherein the second comparator is configured to compare the second bias voltage and the second PTAT voltage and to generate a second comparator output signal based on the comparison, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage; and
a flip-flop electrically coupled to the first comparator and the second comparator, wherein:
the flip-flop is configured to generate a clock signal based on the first and the second comparator output signals,
the first and the second bias voltage generation circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series with a resistor, the PTAT current source being configured to produce a current and provide the current to the resistor,
the PTAT current source comprises a plurality of PMOS transistors and a plurality of NMOS transistors,
the current is characterized by nV t ln(M)/R B , and
V t is the thermal voltage, M is a beta parameter of one of the plurality of PMOS transistors, R B is a bias resistance, and n is a scaling factor.
14 . An on-chip (ULP) RC oscillator, the on-chip ULP RC oscillator comprising:
a first comparator, wherein the first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit, the first bias voltage generation circuit being configured to generate a first bias voltage, and the first capacitor circuit being configured to generate a first proportional to absolute temperature (PTAT) voltage, wherein the first comparator is configured to compare the first bias voltage and the first PTAT voltage, and to generate a first comparator output signal based on the comparison;
a second comparator, wherein the second comparator comprises a first input electrically coupled to a second bias voltage generation circuit and a second input electrically coupled to a second capacitor circuit, the second bias voltage generation circuit being configured to generate a second bias voltage, and the second capacitor circuit being configured to generate a second PTAT voltage, wherein the second comparator is configured to compare the second bias voltage and the second PTAT voltage and to generate a second comparator output signal based on the comparison, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage; and
a flip-flop electrically coupled to the first comparator and the second comparator,
wherein:
the flip-flop is configured to generate a clock signal based on the first and the second comparator output signals,
the first and the second capacitor circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series to an NMOS transistor, a capacitor, and a temperature compensation circuit,
the PTAT current source is configured to produce a current and provide the current to the NMOS transistor and the capacitor,
the temperature compensation circuit comprises a second order current source, and
the second order current source is configured to produce an additional current and provide the additional current to the NMOS transistor and the capacitor.
15 . The on-chip ULP RC oscillator of claim 14 , wherein the additional current directly varies with an operating temperature of the on-chip ULP RC oscillator.
16 . The on-chip ULP RC oscillator of claim 14 , wherein the clock signal comprises a frequency stability of about 5.9 ppm/° C.
17 . A method of generating a clock signal, the method comprising:
generating, by a first bias voltage generation circuit, a first bias voltage;
generating, by a second bias voltage generation circuit, a second bias voltage;
generating, by a first capacitor circuit, a first proportional to absolute temperature (PTAT) voltage;
generating, by a second capacitor circuit, a second PTAT voltage;
comparing, by a first comparator, the first bias voltage and the first PTAT voltage;
generating, by the first comparator, a first comparator output signal based on the comparison of the first bias voltage and the first PTAT voltage;
comparing, by a second comparator, the second bias voltage and the second PTAT voltage;
generating, by the second comparator, a second comparator output signal based on the comparison of the second bias voltage and the second PTAT voltage, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage;
generating, by an RS flip-flop electrically coupled to the first comparator and the second comparator, a clock signal based on the first and the second comparator output signals;
receiving, by a first input of the RS flip-flop, the first comparator output signal;
receiving, by a second input of the RS flip-flop, the second comparator output signal;
providing, by a first output of the RS flip-flop, a first offset correction to the first comparator; and
providing, by a second output of the RS flip-flop, a second offset correction to the second comparator.
18 . The method of claim 17 , wherein the first and the second bias voltage generation circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series with a resistor; and wherein the method further comprises:
producing, by the PTAT current source, a current; and
providing, by the PTAT current source, the current to a resistor, wherein the first and the second bias voltage generation circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series with a resistor.
19 . The method of claim 18 , wherein the PTAT current source is biased sub-threshold.
20 . The method of claim 18 , further comprising producing, by the PTAT current source, a current that is proportional to the thermal voltage.
21 . The method of claim 18 , wherein the PTAT current source comprises a plurality of PMOS transistors and a plurality of NMOS transistors, wherein the current is characterized by nV t ln(M)/R B , and wherein V t is the thermal voltage, M is a beta parameter of one of the plurality of PMOS transistors, R B is a bias resistance, and n is a scaling factor.
22 . The method of claim 18 , wherein the resistor comprises a poly-resistor, and wherein the resistor is characterized by a bias resistance, R B .
23 . The method of claim 17 , wherein the first and the second capacitor circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series to an NMOS transistor, a capacitor, and a temperature compensation circuit; and wherein the method further comprises:
producing, by the PTAT current source, a current, and
providing, by the PTAT current source, the current to the NMOS transistor and the capacitor.
24 . The method of claim 23 , wherein the PTAT current source is biased sub-threshold.
25 . The method of claim 23 , further comprising producing, by the PTAT current source, a current that is proportional to the thermal voltage.
26 . The method of claim 23 , wherein the NMOS transistor is electrically coupled at its source to the capacitor, and the NMOS transistor is electrically coupled at its gate to the flip-flop.
27 . The method of claim 23 , wherein the capacitor is a Metal-Insulator-Metal (MIM) capacitor.
28 . The method of claim 23 , wherein the temperature compensation circuit comprises a second order current source; and wherein the method further comprises:
producing, by the second order current source, an additional current, and
providing, by the second order current source, the additional current to the NMOS transistor and the capacitor.
29 . The method of claim 28 , wherein the additional current directly varies with an operating temperature.
30 . The method of claim 28 , wherein the clock signal comprises a frequency stability of about 5.9 ppm/° C.
31 . The method of claim 17 , wherein the thermal voltage varies with an operating temperature.
32 . The method of claim 17 , wherein the RS flip-flop is electrically coupled to the first capacitor circuit and the second capacitor circuit; and wherein the method further comprises:
driving, by a first output of the RS flip-flop, the second capacitor circuit; and
driving, by a second output of the RS flip-flop, the first capacitor circuit.