Switching converter controller with adaptive pulse-frequency modulation timer circuit

1 . A switching converter controller comprising:

mode control logic; and

a pulse-frequency modulation (PFM) timer circuit coupled to the mode control logic, the PFM timer circuit including:

a first terminal;

a second terminal;

a current source having a first terminal, a second terminal, and a third terminal, the current source configurable to receive a first signal at the second terminal in a first mode and receive a second signal at the second terminal in a second mode, the first signal indicative of a zero valley current, and the second signal indicative of a difference between a feedback voltage and a reference voltage;

a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the current source;

a comparator having a first terminal, a second terminal, and a third terminal, the first terminal of the comparator coupled to the first terminal of the capacitor, and the third terminal of the comparator coupled to the second terminal of the PFM timer circuit.

2 . The switching converter controller of claim 1 , wherein the current source is a first current source, the PFM timer circuit includes:

a second current source having a first terminal, a second terminal, and a third terminal, the third terminal of the second current source coupled to the first terminal of the capacitor; and

a digital-to-analog converter (DAC) having a first terminal and a second terminal, the first terminal of the DAC coupled to the first terminal of the PFM timer circuit, and a second terminal of the DAC coupled to the second terminal of the second current source.

3 . A switching converter controller comprising:

mode control logic; and

a pulse-frequency modulation (PFM) timer circuit coupled to the mode control logic and configured to:

receive a mode control signal;

responsive to the mode control signal, set a current of the PFM timer circuit responsive to one of a first reference voltage or a feedback error voltage;

charge a capacitor responsive to the current;

compare a charge on the capacitor to a second reference voltage to obtain a PFM timer result; and

output the PFM timer result.

4 . The switching converter controller of claim 3 , wherein the PFM timer circuit is configurable to set the current of the PFM timer circuit responsive to the mode control signal, signals representing a set of digital values, and the first reference voltage indicative of a zero valley current.

5 . The switching converter controller of claim 4 , wherein the PFM timer circuit is configured to discharge the capacitor responsive to a second switch control signal.

6 . The switching converter controller of claim 5 , wherein the PFM timer circuit has a third terminal and a fourth terminal, the PFM timer circuit includes a switch having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the switch to receive the first signal, the second terminal of the switch is coupled to the third terminal of the PFM timer circuit, the third terminal of the switch coupled to the fourth terminal of the PFM timer circuit, and the fourth terminal of the switch coupled to the second terminal of the second current source.

7 . The switching converter controller of claim 6 , wherein the switch is a first switch, the PFM timer circuit has a fifth terminal and includes a second switch having a first terminal, a second terminal, and a third terminal, the first terminal of the second switch coupled to the first terminal of the capacitor, and the second terminal of the second switch coupled to the fifth terminal of the PFM timer circuit.

8 . The switching converter controller of claim 7 , wherein the mode control logic has a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the mode control logic coupled to the second terminal of the PFM timer circuit, the second terminal of the mode control logic coupled to the first terminal of the PFM timer circuit, the third terminal of the mode control logic is coupled to the fourth terminal of the PFM timer circuit, and the fourth terminal of the mode control logic is coupled to the fifth terminal of the PFM timer circuit.

9 . The switching converter controller of claim 8 , further comprising an error amplifier having a first terminal, a second terminal, and a third terminal, the third terminal of the error amplifier coupled to the fourth terminal of the PFM timer circuit.

10 . The switching converter controller of claim 9 , further comprising a voltage-to-current converter, a peak comparator, and a valley comparator, the voltage-to-current converter having a first terminal, a second terminal, and a third terminal, the peak comparator having a first terminal, a second terminal, and a third terminal, the valley comparator having a first terminal, a second terminal, and a third terminal, the first terminal of the voltage-to-current converter coupled to the third terminal of the error amplifier, the second terminal of the voltage-to-current converter coupled to the second terminal of the peak comparator, and the third terminal of the voltage-to-current converter coupled to the first terminal of the valley comparator.

11 . The switching converter controller of claim 10 , further comprising driver circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the mode control logic has a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal, the fifth terminal of the mode control logic coupled to the third terminal of the peak comparator, the third terminal of the valley comparator coupled to the sixth terminal of the mode control logic, the seventh terminal of the mode control logic coupled to the first terminal of the driver circuitry, and the eighth terminal of the mode control logic coupled to the second terminal of the driver circuitry.

12 . The switching converter controller of claim 11 , wherein the mode control logic is configured to:

receive a clock signal, a PFM timer result, a peak compare result, and a valley compare result;

adjust a pulse-width modulation (PWM) control signal state and high-impedance control signal state responsive to the clock signal, the PFM timer result, the peak compare result, and the valley compare result;

identify a light load trigger; and

provide adaptation control signals to the PFM timer circuit responsive to the light load trigger.

13 . The switching converter controller of claim 3 , further comprising mode control logic configured to:

receive a light load signal;

provide adaptation control signals to the PFM timer circuit responsive to the light load signal;

monitor adaptation results of the PFM timer circuit responsive to the adaptation control signals; and

transition to a PFM mode responsive to the adaptation results indicating PFM timing is aligned with a target PFM timing.

14 . The switching converter controller of claim 4 , further comprising an error amplifier configured to provide the feedback error voltage responsive to an output voltage and a reference voltage.

15 . The switching converter controller of claim 5 , further comprising mode control logic configured to provide the mode control signal, the signals, and a switch control signal.

16 . A system comprising:

a power stage; and

a switching converter controller coupled to the power stage, the switching converter controller configurable to:

operate the power stage in a first mode, in which a period of a switching cycle is set by a clock signal in the first mode;

receive a trigger signal;

responsive to receiving the trigger signal, transition the power stage to a second mode, in which a period of a switching cycle in the second mode is equal to the period of the switching cycle in the first mode; and

after the transition, vary the period of the switching cycle the second mode to set an output current of the power stage.

17 . The system of claim 16 , wherein the second mode is a pulse frequency modulation (PFM) mode, and the switching converter controller includes a PFM timer circuit configurable to:

receive a mode control signal;

adjust a current of the PFM timer circuit responsive to the mode control signal;

charge a capacitor responsive to the adjust current;

compare a charge on the capacitor to a reference voltage to obtain a PFM timer result; and

responsive to the PFM timer result, transition to the PFM.

18 . The system of claim 17 , wherein the PFM timer circuit is configurable to adjust the current of the PFM timer circuit responsive to the mode control signal.

19 . The system of claim 18 , wherein the PFM timer circuit includes a digital-to-analog converter (DAC), a first current source, and a second current source, the first current source is configured to provide a first current responsive to the switch control signal, the DAC is configurable to provide an analog signal responsive to a digital control signal, and the second current source is configurable to adjust the first current responsive to the analog signal.

20 . The system of claim 19 , wherein the first mode is a pulse width modulation (PWM) mode having a zero valley current, and the first current source is configured to provide a current, to the PFM timer circuit responsive to a zero valley reference voltage representing the zero valley current.