Semiconductor device
A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.
1 . A semiconductor device comprising:
a substrate which includes a first surface and a second surface opposite to the first surface;
a first power supply line formed on the second surface;
a second power supply line formed on the second surface;
a first ground line formed on the first surface;
a third power supply line formed on the first surface and electrically connected to the first power supply line;
a fourth power supply line formed on the first surface and electrically connected to the second power supply line;
one or more vias formed in the substrate and connecting the first power supply line and the third power supply line,
a first area in which the first ground line and the fourth power supply line are arranged;
a first circuit connected between the first ground line and the third power supply line; and
a switch is connected between the first power supply line and the second power supply line,
wherein,
in a plan view, the third power supply line, the one or more vias, and the first circuit are arranged in the first area.
2 . The semiconductor device according to claim 1 , wherein the switch is formed on the second surface.
3 . The semiconductor device according to claim 1 ,
wherein
the switch includes a gate electrode;
the first circuit is connected to the gate electrode.
4 . The semiconductor device according to claim 3 ,
wherein the fourth power supply line includes
a first power supply line strip extending in a first direction in plan view;
a second power supply line strip extending in the first direction at a distance from the first power supply line strip; and
the third power supply line is arranged between the first power supply line strip and the second power supply line strip at a distance from the first power supply line strip and the second power supply line strip.
5 . The semiconductor device according to claim 3 ,
wherein the fourth power supply line includes
a first power supply line strip extending in a first direction in plan view;
a second power supply line strip extending in the first direction at a distance from the first power supply line strip; and
a connection is provided between the first power supply line strip and the second power supply line strip at a distance from the first power supply line strip and the second power supply line strip, and connected between the first circuit and the gate electrode.
6 . The semiconductor device according to claim 3 ,
wherein the fourth power supply line includes
a first power supply line strip extending in a first direction in plan view, and
a second power supply line strip extending in the first direction at a distance from the first power supply line strip;
the third power supply line is arranged between the first power supply line strip and the second power supply line strip at a distance from the first power supply line strip and the second power supply line strip;
and
the first chip includes a connection provided between the first power supply line strip and the second power supply line strip at a distance from the first power supply line strip and the second power supply line strip, and connected between the first circuit and the control terminal.
7 . The semiconductor device according to claim 1 , further comprising
a third ground line formed on the first surface,
a fifth power supply line formed on the first surface and connected to the first power supply line, and
a second area in which the third ground line and the fifth power supply line are arranged in plan view.
8 . The semiconductor device according to claim 7 , further comprising a second circuit connected between the third ground line and the fifth power supply line, and connected to the first circuit.
9 . The semiconductor device according to claim 1 , further comprising
a sixth power supply line formed on the first surface; and
a third circuit formed on the first surface and connected between the first ground line and the sixth power supply line,
wherein the third circuit is arranged in the first area in a plan view.
10 . The semiconductor device according to claim 9 , wherein power supply potential supplied to the sixth power supply line is equal to a power supply potential supplied to the first power supply line.
11 . The semiconductor device according to claim 9 , wherein a power supply potential supplied to the sixth power supply line is different from a power supply potential supplied to the first power supply line.
12 . The semiconductor device according to claim 1 , wherein the switch includes
a semiconductor layer connected to the first power supply line and the second power supply line,
a gate electrode, and
a gate insulating film provided between the semiconductor layer and the gate electrode.
13 . The semiconductor device according to claim 12 ,
wherein the gate insulating film is formed on a surface of the semiconductor layer that faces the substrate; and
wherein the gate electrode is formed on a surface of the gate insulating film that faces the first substrate.
14 . The semiconductor device according to claim 12 ,
wherein the gate insulating film is formed on a surface of the semiconductor layer opposite a surface of the semiconductor layer that faces the substrate; and
wherein the gate electrode is formed on a surface of the gate insulating film opposite a surface of the gate insulating film that faces the substrate.
15 . The semiconductor device according to claim 1 , further comprising
a mounting substrate on which the substrate;
wherein the switch is arranged on the mounting substrate at a position different from positions of the substrate.
16 . The semiconductor device according to claim 3 ,
further comprising a plurality of the switches;
wherein the first circuit is connected to the gate electrode of each of the plurality of switches.
17 . The semiconductor device according to claim 3 ,
further comprising a plurality of the switches and a plurality of the first circuits;
wherein the plurality of first circuits are respectively connected to the gate electrodes of the plurality of switches.
18 . The semiconductor device according to claim 1 ,
further comprising a plurality of the switches arranged in a grid pattern in plan view.
19 . The semiconductor device according to claim 18 , wherein
each of the switches includes a source, a drain and a gate electrode;
the sources are electrically connected by the first power supply line; and
the drains are electrically connected by the second power supply line.
20 . The semiconductor device according to claim 19 , further comprising a plurality of the first power supply lines and a plurality of the second power supply lines,
wherein
each of the first power supply lines extends in a first direction in plan view;
each of the second power supply lines extends in the first direction in plan view;
the first power supply lines and the second power supply lines are arranged in a second direction different from the first direction in plan view;
the first power supply lines are electrically connected each other; and
the second power supply lines are electrically connected each other.