3D splintered physically unclonable function (3D-sPUF)
Embodiments herein describe a 3D splintered physical unclonable function (3D-sPUF). In an example, an integrated circuit (IC) device includes multiple dies in a stacked configuration, and a PUF circuit generates a set of bits that is unique to the PUF circuit based on physical variations of elements of the PUF circuit, where the PUF circuit is distributed amongst two or more of the dies.
1 . An integrated circuit (IC) device, comprising:
a first metal layer comprising first and second power supply nodes;
a second metal layer comprising first and second ground nodes;
multiple dies in a stacked configuration, disposed between first and second metal layers; and
a physical unclonable function (PUF) circuit configured to generate a set of bits that is unique to the IC device based on physical variations of elements of the PUF circuit;
wherein the PUF circuit is distributed amongst two or more of the dies; and
wherein the PUF circuit comprises power supply circuitry that comprises:
a first power supply path between the first power supply node and the first ground node and through the multiple dies; and
a second power supply path between the second power supply node and the second ground node and through the multiple dies.
2 . The IC device of claim 1 , wherein:
the PUF circuit further comprises bit generator circuitry configured to generate the set of bits based on the physical variations of elements of the PUF circuit, including physical variations of elements of the bit generator circuitry;
the power supply circuitry is configured to provide power to the bit generator circuitry; and
one or more of the bit generator circuitry and the power supply circuitry is distributed amongst the two or more dies.
3 . The IC device of claim 2 , wherein the bit generator circuitry is disposed in one of the dies, and wherein the power supply circuitry is distributed amongst the two or more dies.
4 . The IC device of claim 2 , wherein the bit generator circuitry is distributed amongst the two or more dies.
5 . The IC device of claim 2 , wherein the bit generator circuitry is configured to generate the set of bits based further on a physical variation of an element of the power supply circuitry.
6 . The IC device of claim 5 , wherein:
the power supply circuitry comprises a path through two or more of the dies;
the path comprises one or more resistors; and
the bit generator circuitry is configured to generate the set of bits based further on a physical variation of the one or more resistors.
7 . The IC device of claim 2 , wherein:
the power supply circuitry further comprises a resistor in the first power supply path configured to reduce a voltage of the first power supply node, and a current bias circuit configured to control a current of the second power supply path based on the reduced voltage of the first power supply node;
the resistor and the current bias circuit are disposed in different ones of the dies; and
the bit generator circuitry is configured to generate the set of bits based further on a physical variation of the resistor.
8 . The IC device of claim 7 , wherein the current bias circuit is disposed in one of:
a first one of the dies adjacent to the first metal layer; and
a second one of the dies adjacent to the second metal layer.
9 . The IC device of claim 7 , wherein:
the current bias circuit is disposed in an intermediate one of the dies that is positioned between a first one of the dies adjacent to the first metal layer, and a second one of the dies adjacent to the second metal layer;
one or more of the first and second paths further comprises a switch; and
one or more of the first die and the second die comprises circuitry configured to control the switch.
10 . The IC device of claim 2 , wherein:
the power supply circuitry comprises a path through the dies;
the path comprises a switch disposed in an intermediate one of dies positioned between a top one of the dies and a base one of the dies; and
one or more of the top die and the base die comprises circuitry configured to control the switch.
11 . The IC device of claim 2 , wherein:
the dies comprise a first set of one or more dies fabricated based on a first fabrication process, and a second set of one or more dies fabricated based on a second fabrication process that differs from the first fabrication process; and
the bit generator circuitry is disposed in one or more dies of the first set of one or more dies; and
the power supply circuitry is distributed amongst the first and second sets of dies.
12 . The IC device of claim 2 , wherein:
the bit generator circuitry comprises a set of bit generator circuits; and
the bit generator circuitry is configured to use a selectable subset of the set of bit generator circuits to generate the set of bits.
13 . The IC device of claim 2 , wherein:
the multiple dies are disposed between first and second metal layers;
the power supply circuitry comprises first and second power supply paths between a voltage supply of the first metal layer and a reference voltage the second metal layer;
the IC device further comprises a shielding layer, wherein one of the first and second metal layers is disposed between the shielding layer and the dies; and
the shielding layer comprises a portion of one or more of the first and second power supply paths.
14 . The IC device of claim 1 , wherein:
the power supply circuitry comprises a path that extends through two or more of the dies;
the path comprises metal-filled vias of dielectric layers positioned between adjacent ones of the two or more dies; and
the sources of entropy further comprise physical variations of the metal-filled vias.
15 . A system, comprising:
a first device comprising an integrated circuit (IC) device, wherein the IC device comprises:
a first metal layer comprising first and second power supply nodes;
a second metal layer comprising first and second ground nodes;
multiple dies in a stacked configuration, disposed between first and second metal layers;
a physical unclonable function (PUF) circuit configured to generate a set of bits that is unique to the IC device based on physical variations of elements of the PUF circuit, wherein:
the PUF circuit is distributed amongst two or more of the dies;
the PUF circuit comprises power supply circuitry that comprises:
a first power supply path between the first power supply node and the first ground node and through the multiple dies; and
a second power supply path between the second power supply node and the second ground node and through the multiple dies; and
digital processing circuitry configured to generate a multi-bit key based on the set of bits; and
a second device, external of the first device, configured to perform one or more of:
authenticate the first device based on the multi-bit key;
generate an encryption key based on the multi-bit key; and
encrypt data based on the multi-bit key.
16 . The system of claim 15 , wherein:
the PUF circuit further comprises: bit generator circuitry configured to generate the set of bits based on the physical variations of the elements of the PUF circuit;
the power supply circuitry is configured to provide power to the bit generator circuitry; and
one or more of the bit generator circuitry and the power supply circuitry is distributed amongst the two or more dies.
17 . The system of claim 16 , wherein the bit generator circuitry is configured to generate the set of bits based further on a physical variation of an element of the power supply circuitry.
18 . The system of claim 17 , wherein:
the power supply circuitry further comprises a resistor in the first power supply path configured to reduce a voltage of the first power supply node, and a current bias circuit configured to control a current of the second power supply path based on the reduced voltage of the first power supply node;
the resistor and the current bias circuit are disposed in different ones of the dies; and
the bit generator circuitry is configured to generate the set of bits based further on a physical variation of the resistor.
19 . An apparatus, comprising:
a processor and a memory comprising instructions to cause the processor to;
apply power to an integrated circuit (IC) device that comprises multiple dies in a stacked configuration and a physical unclonable function (PUF) circuit that comprises multiple bit generator circuits configured to generate respective bit values based on physical variations of elements of the PUF circuit, wherein the PUF circuit is distributed amongst two or more of the dies;
capture the bit values generated by the bit generator circuits;
select a subset of the bit generator circuits based on stabilities of the captured bit values; and
configure the PUF circuit to use the selected subset of bit generator circuits to generate a set of bit values when power is subsequently applied to the IC device.
20 . The apparatus of claim 19 , wherein:
the PUF circuit further comprises power supply circuitry configured to provide power to the bit generator circuits; and
the bit generator circuits are configured to generate the respective bit values based further on a physical variation of an element of the power supply circuitry.