Interconnect structures for integration of memory cells and logic cells
A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.
1 . A semiconductor structure, comprising:
a memory cell electrically coupled to a bit line, a bit line bar, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electric ground voltage;
one or more logic cells configured to provide logic function to the memory cell, the memory cell spaced apart from the one or more logic cells along a first direction; and
an interconnect structure disposed over the memory cell and the one or more logic cells,
wherein:
the interconnect structure includes the bit line, the bit line bar, the first voltage line, the second voltage line, and a pad all located in a same metal line layer of the interconnect structure,
at least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell,
one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and through the boundary of the memory cell,
another one of the first and second voltage lines is aligned with the pad along the first direction and electrically coupled to the pad, and
when viewed from top the pad overlaps with the memory cell.
2 . The semiconductor structure of claim 1 , wherein the memory cell is a static random-access memory (SRAM) cell.
3 . The semiconductor structure of claim 1 , wherein the boundary of the memory cell directly abuts the boundary of the one or more logic cells.
4 . The semiconductor structure of claim 1 , wherein the bit line fully extends through the memory cell.
5 . The semiconductor structure of claim 4 , wherein the bit line bar fully extends through the memory cell.
6 . The semiconductor structure of claim 1 , wherein the first voltage line fully extends through the memory cell.
7 . The semiconductor structure of claim 6 , wherein the second voltage line fully extends through the memory cell.
8 . The semiconductor structure of claim 6 , wherein the first voltage line has a uniform width inside the boundary of the one or more logic cells and a varied width inside the boundary of the memory cell.
9 . The semiconductor structure of claim 1 , wherein the interconnect structure includes a metal line located in the metal line layer, the metal line extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell, and the metal line is functional for the one or more logic cells and non-functional for the memory cell.
10 . The semiconductor structure of claim 1 , wherein the metal line layer includes a plurality of metal tracks inside the boundary of the one or more logic cells, wherein the first voltage line is located in a center one of the plurality of metal tracks, and the bit line and the bit line bar are evenly spaced from the first voltage line.
11 . The semiconductor structure of claim 10 , wherein a number of the plurality of metal tracks inside the boundary of the one or more logic cells is an odd number.
12 . A semiconductor structure, comprising:
a memory cell;
a logic cell abutting the memory cell along a first direction; and
an interconnect structure disposed over the memory cell and the logic cell,
wherein:
the interconnect structure includes a bottommost metal line layer that includes a first signal line, a second signal line, a power supply line, and an electric ground line,
the first signal line extends from the logic cell and through the memory cell as a straight line along the first direction and maintaining within the bottommost metal line layer,
the second signal line remains within the logic cell, and
the electric ground line extends from the logic cell and into the memory cell.
13 . The semiconductor structure of claim 12 , wherein the first signal line is a bit line.
14 . The semiconductor structure of claim 13 , wherein the first signal line fully extends through the memory cell.
15 . The semiconductor structure of claim 13 , wherein the first signal line merges with a landing pad for the bit line in the memory cell.
16 . The semiconductor structure of claim 12 , wherein the electric ground line fully extends through the memory cell.
17 . The semiconductor structure of claim 12 , wherein the power supply line extends from the logic cell and fully extends through the memory cell.
18 . A semiconductor structure, comprising:
a memory cell having a plurality of first metal tracks in parallel and spaced apart along a first direction; and
two logic cells abutting each other along the first direction, the two logic cells having a plurality of second metal tracks in parallel and spaced apart along the first direction,
wherein:
each of the first metal tracks is aligned with one of the second metal tracks,
a total number of the second metal tracks is an odd number,
counting along the first direction in sequence the second metal tracks include a first one of the second metal tracks that is an electric ground line and a center one of the second metal tracks that is a power supply line extending through the memory cell, and
a total number of the second metal tracks sandwiched between the electric ground line and the power supply line is an even number.
19 . The semiconductor structure of claim 18 , wherein the second metal tracks include a first signal line and a second signal line each extend through the memory cell.
20 . The semiconductor structure of claim 19 , wherein the power supply line is positioned between the first and second signal lines, and the first and second signal lines are evenly spaced from the power supply line.