Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.
1 . A semiconductor device comprising:
a gate structure including stacked gate lines;
an insulating core located in the gate structure and including a first long axis and a first short axis;
a memory layer surrounding the insulating core;
a first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and
a capping layer including a second short axis and a second long axis, the capping layer located between the first channel pattern and the second channel pattern and protruding beyond both the first channel pattern and the second channel pattern along the second short axis.
2 . The semiconductor device of claim 1 , wherein the insulating core comprises:
a first body including the first long axis and the first short axis and protruding beyond both the first channel pattern and the second channel pattern along the first short axis;
a first protrusion protruding from the first body toward the first channel pattern; and
a second protrusion protruding from the first body toward the second channel pattern.
3 . The semiconductor device of claim 1 , wherein the capping layer comprises:
a second body extending along the second long axis and the second short axis;
a first protruding pattern protruding from the second body toward the first channel pattern; and
a second protruding pattern protruding from the second body toward the second channel pattern.
4 . The semiconductor device of claim 3 , wherein the second body protrudes beyond both the first channel pattern and the second channel pattern and into the memory layer.
5 . The semiconductor device of claim 3 , wherein the memory layer includes a tunneling layer, a data storage layer, and a blocking layer, and the second body extends beyond both the first channel pattern and the second channel pattern and to the data storage layer through the tunneling layer.
6 . The semiconductor device of claim 3 , wherein the memory layer includes a tunneling layer, a data storage layer, and a blocking layer, and the second body extends beyond both the first channel pattern and the second channel pattern and to the blocking layer through the tunneling layer and the data storage layer.
7 . The semiconductor device of claim 3 , wherein at least one of the first channel pattern and the second channel pattern includes a tip partially surrounding the second body.
8 . The semiconductor device of claim 7 , wherein the tip extends along a curved surface of the second body.
9 . The semiconductor device of claim 1 , further comprising:
a bit line connected to the first channel pattern and the second channel pattern through the capping layer.
10 . The semiconductor device of claim 9 , wherein the gate lines comprise:
a first drain select line configured to control a connection between the first channel pattern and the bit line; and
a second drain select line configured to control a connection between the second channel pattern and the bit line.
11 . The semiconductor device of claim 1 , further comprising:
a first barrier pattern located between the first channel pattern and the insulating core; and
a second barrier pattern located between the second channel pattern and the insulating core.
12 . The semiconductor device of claim 11 , wherein the first barrier pattern and the second barrier pattern are separated from each other and are located facing each other along the first long axis.
13 . The semiconductor device of claim 11 , wherein the first barrier pattern includes oxide.
14 . A semiconductor device comprising:
a first memory string including a first channel pattern;
a second memory string adjacent to the first memory string in a first direction and including a second channel pattern;
an insulating core located between the first channel pattern and the second channel pattern, and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being larger than the second width;
a bit line connected to the first memory string and the second memory string;
a first drain select line configured to control a connection between the first memory string and the bit line; and
a second drain select line configured to control a connection between the second memory string and the bit line.
15 . The semiconductor device of claim 14 , wherein the insulating core protrudes beyond both the first channel pattern and the second channel pattern in the second direction, and separates the first channel pattern and the second channel pattern from each other.
16 . The semiconductor device of claim 14 , further comprising:
a capping layer including a body located between the first channel pattern and the second channel pattern, a first protruding pattern protruding from the body toward the first channel pattern, and a second protruding pattern protruding from the body toward the second channel pattern, the capping layer being connected to the first channel pattern and the second channel pattern.
17 . The semiconductor device of claim 16 , wherein the body of the capping layer includes a long axis and a short axis, and the first protruding pattern and the second protruding pattern are located facing each other along the long axis.