Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates with etch back process
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.
1 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.
2 . The integrated circuit structure of claim 1 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.
3 . The integrated circuit structure of claim 2 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.
4 . An integrated circuit structure, comprising:
a first fin;
a second fin;
a first gate stack over the first fin;
a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.
5 . The integrated circuit structure of claim 4 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first fin; and
a second pair of epitaxial source or drain structures at first and second ends of the second fin.
6 . The integrated circuit structure of claim 5 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.
7 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.
8 . The computing device of claim 7 , further comprising:
a memory coupled to the board.
9 . The computing device of claim 7 , further comprising:
a communication chip coupled to the board.
10 . The computing device of claim 7 , wherein the component is a packaged integrated circuit die.
11 . The computing device of claim 7 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
12 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first fin;
a second fin;
a first gate stack over the first fin;
a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; and
a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.
13 . The computing device of claim 12 , further comprising:
a memory coupled to the board.
14 . The computing device of claim 12 , further comprising:
a communication chip coupled to the board.
15 . The computing device of claim 12 , wherein the component is a packaged integrated circuit die.
16 . The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.