Different poly pitches for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.
1 . An integrated circuit structure, comprising:
a first plurality of logic gate structures over a first plurality of fins, the first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures, wherein individual ones of the first plurality of logic gate structures have a gate electrode having a first width; and
a second plurality of logic gate structures over a second plurality of fins, the second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures, the second pitch greater than the first pitch, wherein individual ones of the second plurality of logic gate structures have a gate electrode having a second width the same as the first width, wherein a third pitch between neighboring ones of the second plurality of logic gate structures and the first plurality of logic gate structures is greater than two times but less than three times the second pitch.
2 . The integrated circuit structure of claim 1 , wherein the second pitch is 5% and 25% greater than the first pitch.
3 . The integrated circuit structure of claim 1 , wherein the second pitch is less than 50% greater than the first pitch.
4 . The integrated circuit structure of claim 1 , wherein the first pitch is about 54 nm, and the second pitch is about 60 nm.
5 . The integrated circuit structure of claim 1 , wherein the first width is 10 nm or less.
6 . An integrated circuit structure, comprising:
a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures, wherein individual ones of the first plurality of logic gate structures have a first width; and
a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures, the second pitch greater than the first pitch, wherein individual ones of the second plurality of logic gate structures have a second width less than the first width, wherein a third pitch between neighboring ones of the second plurality of logic gate structures and the first plurality of logic gate structures is greater than two times but less than three times the second pitch.
7 . The integrated circuit structure of claim 6 , wherein the second pitch is 5% and 25% greater than the first pitch.
8 . The integrated circuit structure of claim 6 , wherein the second pitch is less than 50% greater than the first pitch.
9 . The integrated circuit structure of claim 6 , wherein the first pitch is about 54 nm, and the second pitch is about 60 nm.
10 . The integrated circuit structure of claim 1 , wherein the first width is 10 nm or less, and the second width is 10 nm or less.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first plurality of logic gate structures over a first plurality of fins, the first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures, wherein individual ones of the first plurality of logic gate structures have a gate electrode having a first width; and
a second plurality of logic gate structures over a second plurality of fins, the second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures, the second pitch greater than the first pitch, wherein individual ones of the second plurality of logic gate structures have a gate electrode having a second width the same as the first width, wherein a third pitch between neighboring ones of the second plurality of logic gate structures and the first plurality of logic gate structures is greater than two times but less than three times the second pitch.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , further comprising:
a camera coupled to the board.
15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures, wherein individual ones of the first plurality of logic gate structures have a first width; and
a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures, the second pitch greater than the first pitch, wherein individual ones of the second plurality of logic gate structures have a second width less than the first width, wherein a third pitch between neighboring ones of the second plurality of logic gate structures and the first plurality of logic gate structures is greater than two times but less than three times the second pitch.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , further comprising:
a camera coupled to the board.
20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.