IP Library › Granted Patent US 12,660,528
Granted Patent B2
US 12,660,528 · App. 18/468,554 · Granted Jun 16, 2026

Methods for fabricating protected electrode arrays with initial interposer bonding

Inventors: Ryan Nicholl (San Diego, CA); David Pain (Oceanside, CA); Andrew Edmonds (Oceanside, CA); Kareemullah Shaik (San Diego, CA); Edward White (San Diego, CA)
Assignee: Fabric8Labs, Inc.
H10P14/6336H10P14/3411H10P50/283H10P72/0418H10P72/0604H10P72/74H10W70/095B33Y10/00
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Quick Facts
Patent No.
US 12,660,528
App. No.
18/468,554
Granted
Jun 16, 2026
Kind
B2
Abstract

Described herein are protected electrode arrays and methods of fabricating thereof. Such electrode arrays can be used in electrochemical-additive manufacturing (ECAM) systems and other systems/applications. In some examples, a protected electrode array comprises an electrode-interface circuit and an interposer bonded to the circuit, e.g., using an adhesive layer. The interposer can include an interposer base formed from silicon, glass, and other like materials suitable for operating environments. The interposer base comprises vias, which are aligned with the circuit's electrode connectors, and interposer electrodes deposited within these vias and electrically coupled to the electrode connectors. In some examples, the interposer comprises a base cover and/or electrode covers positioned over the interposer base and the interposer electrodes, respectively. The interposer can be bonded to the electrode-interface circuit before forming the vias, after forming the vias but before depositing the interposer electrodes, or after depositing the interposer electrodes within the vias.

Claims (42)

1 . A method of fabricating a protected electrode array assembly, the method comprising:

forming a passivation layer on an interposer base;

bonding the interposer base to an electrode interface circuit using an adhesive layer, wherein:

the electrode interface circuit comprises a circuit base and electrode connectors supported within the circuit base, and

the adhesive layer is positioned between the circuit base and the interposer base;

after bonding the interposer base, forming vias in the interposer base using a technique comprising:

a plasma etch step of directing plasma to the interposer base thereby creating a trench comprising a bottom and side walls,

a deposition step of depositing a chemically inert passivation layer on the side walls and the bottom of the trench, and

repeating the plasma etch step and the deposition step until the vias are formed; and

after forming the vias, depositing interposer electrodes at least partially within the vias in the interposer base thereby forming the interposer, which is a part of the protected electrode array assembly, wherein each of the electrode connectors is electrically coupled and mechanically attached to the interposer electrodes after depositing the interposer electrodes.

2 . The method of claim 1 , wherein the passivation layer is formed using thermal oxidation of the interposer base.

3 . The method of claim 1 , wherein:

the interposer base comprises a primary surface and a secondary surface, opposite to the primary surface, and

the passivation layer is formed on at least a secondary surface.

4 . The method of claim 3 , wherein the passivation layer is also formed on a primary surface, opposite of the secondary surface.

5 . The method of claim 4 , further comprising, prior to forming the vias in the interposer base, removing the passivation layer from the primary surface.

6 . The method of claim 5 , wherein the passivation layer on the secondary surface is retained after removing the passivation layer from the primary surface.

7 . The method of claim 5 , further comprising, after removing the passivation layer from the primary surface, depositing a second passivation layer on the primary surface using plasma-enhanced chemical vapor deposition (PECVD).

8 . The method of claim 1 , wherein, after forming the vias in the interposer base, the vias extend to but not through the adhesive layer.

9 . The method of claim 8 , further comprising, after forming the vias in the interposer base, removing portions of the adhesive layer exposed in the vias thereby exposing the electrode connectors of the electrode interface circuit within the vias.

10 . The method of claim 9 , wherein removing the portions of the adhesive layer exposed in the vias comprises one of (a) etching the portions of the adhesive layer and (b) dissolving the portions of the adhesive layer.

11 . The method of claim 1 , further comprising, after forming the vias in the interposer base,

forming a third passivation layer at least on sidewalls of the vias using plasma-enhanced chemical vapor deposition (PECVD), and

etching portions of the third passivation layer at bottoms of the vias thereby exposing the electrode connectors of the electrode interface circuit within the vias.

12 . The method of claim 1 , wherein:

the plasma in the plasma etch step is formed using sulfur hexafluoride (SF 6 ), and

the chemically inert passivation layer comprises a fluorocarbon.

13 . The method of claim 1 , wherein the interposer base comprises one or more materials selected from the group consisting of silicon, glass, sapphire, silicon nitride, silicon dioxide, silicon oxynitride, and aluminum oxide.

14 . The method of claim 1 , wherein the interposer base comprises glass.

15 . The method of claim 1 , wherein the interposer base comprises silicon.

16 . The method of claim 1 , wherein depositing the interposer electrodes comprises:

sputtering a seed layer at least partially extending into the vias and over a surface of the interposer base; and

electroplating the interposer electrodes into the vias.

17 . The method of claim 16 , wherein depositing the interposer electrodes further comprises polishing off the surface of the interposer base thereby removing a portion of the interposer electrodes extending over the surface of the interposer base.

18 . The method of claim 16 , wherein depositing the interposer electrodes comprises:

prior to electroplating the interposer electrodes into the vias, filing the vias with temporary plugs,

removing a portion of the seed layer extending over the surface of the interposer base, and

removing the temporary plugs from the vias.

19 . The method of claim 1 , further comprising depositing a base cover, wherein:

the base cover comprises electrode openings, exposing a portion of the interposer electrodes, and

the interposer base is positioned between the base cover and electrode interface circuit.

20 . The method of claim 1 , further comprising, prior to depositing the interposer electrodes, removing a portion of the interposer base.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2023
From: NICHOLL, RYAN; PAIN, DAVID; EDMONDS, ANDREW; SHAIK, KAREEMULLAH; WHITE, EDWARD
To: FABRIC8LABS, INC.
Reel/Frame 065175/0127 →
Continuity (2)
Provisional Application 63488588 · Mar 6, 2023
Related Publication 20240304440A1 · Sep 12, 2024
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