IP Library Granted Patent US 12,660,587
Granted Patent B2
US 12,660,587 · App. 18/224,489 · Granted Jun 16, 2026

Semiconductor device

Inventors: Yi-Ren Chen (Hsinchu, TW); Po-Cheng Chi (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10W20/20H10D30/43H10D30/6735H10D30/6757H10D62/121
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,660,587
App. No.
18/224,489
Granted
Jun 16, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. The oxide definition structures are formed on the substrate and arranged in a first direction. The metal gates are formed on the substrate and extend in a second direction. The first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. There is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.

Claims (52)

1 . A semiconductor device, comprising:

a substrate;

a plurality of oxide definition (OD) structures formed on the substrate and arranged in a first direction;

a plurality of metal gates formed on the substrate and extending in the first direction; and

a first conductive via formed on the substrate, located between two of the metal gates, extending in the first direction and having a first width in a second direction;

wherein there is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7;

wherein the semiconductor device further comprises:

a second conductive via formed above the first conductive via;

wherein the first conductive via has a base width in the second direction, and a second ratio of the first width to the base width ranges between 0.5 and 0.99.

2 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a first portion having the first width, and the semiconductor device further comprises:

an oxide layer formed below the first portion of the first conductive via.

3 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a first portion having the first width, and the semiconductor device further comprises:

an epitaxy layer formed below the first portion of the first conductive via.

4 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a base portion having the base width, and the semiconductor device further comprises:

an epitaxy layer formed below the base portion of the first conductive via.

5 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a first portion having the first width, and the second conductive via and the first portion are staggered in the first direction.

6 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a first portion having the first width and a second portion;

wherein the first portion and the second portion are located at two opposite sides of the second conductive via respectively in the first direction.

7 . The semiconductor device as claimed in claim 1 , wherein the first conductive via comprises a first portion having the first width and a second portion having a second width, the first portion is separated from the second portion, and the first width is different from the second width.

8 . A semiconductor device, comprising:

a substrate;

a plurality of OD structures formed on the substrate and arranged in a first direction;

a plurality of metal gates formed on the substrate and extending in the first direction; and

a first conductive via formed on the substrate, located between two of the metal gates, extending in the first direction and comprising a first portion and a base portion;

wherein the base portion has a first lateral surface, and the first portion has a second lateral surface recessed with respect to the first lateral surface;

wherein the semiconductor device further comprises:

a second conductive via formed above the first conductive via;

wherein the first conductive via has a first width in the second direction, the first conductive via has a base width in a second direction, and a second ratio of the first width to the base width ranges between 0.5 and 0.99.

9 . The semiconductor device as claimed in claim 8 , wherein the first portion has a first width in the second direction, there is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.

10 . The semiconductor device as claimed in claim 8 , further comprising:

an oxide layer formed below the first portion of the first conductive via.

11 . The semiconductor device as claimed in claim 8 , wherein the semiconductor device further comprises:

an epitaxy layer formed below the first portion of the first conductive via.

12 . The semiconductor device as claimed in claim 8 , wherein the first conductive via comprises a base portion having the base width, and the semiconductor device further comprises:

an epitaxy layer formed below the base portion of the first conductive via.

13 . The semiconductor device as claimed in claim 8 , wherein the second conductive via and the first portion are staggered in the first direction.

14 . The semiconductor device as claimed in claim 8 , wherein the first conductive via further comprises a second portion,

and the first portion and the second portion are located at two opposite sides of the second conductive via respectively in the first direction.

15 . The semiconductor device as claimed in claim 8 , wherein the second lateral surface is a curved surface, a flat surface and a combination thereof.

16 . A semiconductor device, comprising:

a substrate;

a plurality of OD structures formed on the substrate and arranged in a first direction;

a plurality of metal gates formed on the substrate and extending in the first direction;

a first conductive via formed on the substrate, located between two of the metal gates, extending in the first direction and comprising a first portion;

a second conductive via formed above and connected with the first conductive via; and

an epitaxy layer formed below the first conductive via;

wherein the first portion is staggered with the epitaxy layer and the second conductive via in the first direction;

wherein the first conductive via has a base width in a second direction, and a second ratio of the first width to the base width ranges between 0.5 and 0.99.

17 . The semiconductor device as claimed in claim 16 , wherein the first portion has a first width in the second direction, the second conductive via has a via width, the first width is less than the via width.

18 . The semiconductor device as claimed in claim 17 , wherein the base width is greater than the first width and the via width.

19 . The semiconductor device as claimed in claim 16 , wherein the first conductive via comprises a base portion having the base width, and the epitaxy layer is formed below the base portion of the first conductive via.

20 . The semiconductor device as claimed in claim 16 , wherein the first conductive via further comprises a second portion, and the first portion and the second portion are located at two opposite sides of the second conductive via respectively in the first direction.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE INVENTOR EXECUTION DATES PREVIOUSLY RECORDED AT REEL: 064332 FRAME: 0498. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Jan 3, 2024
From: CHEN, YI-REN; CHI, PO-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 066172/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2023
From: CHEN, YI-REN; CHI, PO-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 064332/0498 →
Continuity (1)
Related Publication 20250029893A1 · Jan 23, 2025
References Cited (2)
US 20200135869A1 · Ciou · 2020 [cited by examiner]
US 20220415782A1 · Choi · 2022 [cited by examiner]