IP Library Granted Patent US 12,666,747
Granted Patent B2
US 12,666,747 · App. 18/594,924 · Granted Jun 23, 2026

Solid-state imaging device and electronic apparatus

Inventors: Reijiroh Shohji (Nagasaki, JP); Masaki Haneda (Kanagawa, JP); Hiroshi Horikoshi (Kanagawa, JP); Minoru Ishida (Tokyo, JP); Takatoshi Kameshima (Kanagawa, JP); Ikue Mitsuhashi (Kanagawa, JP); Hideto Hashiguchi (Kanagawa, JP); Tadashi Iijima (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10F39/811H10F39/809H10W20/20H10W90/792
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Quick Facts
Patent No.
US 12,666,747
App. No.
18/594,924
Filed
Mar 4, 2024
Granted
Jun 23, 2026
Kind
B2
Art Unit
2891
USPC
257/443
Abstract

There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.

Claims (30)

1 . A light detecting device, comprising:

a first structure including a first semiconductor substrate and a first insulating layer, the first semiconductor substrate having a plurality of pixels;

a second structure including a second semiconductor substrate, a second insulating layer, and a third insulating layer; and

a third structure including a third semiconductor substrate and a fourth insulating layer,

wherein the first structure and the second structure are bonded together such that the first insulating layer and the second insulating layer are adjacent to each other, and

wherein the second structure and the third structure are bonded together such that the third insulating layer and the fourth insulating layer are adjacent to each other;

a first via that passes through the second semiconductor substrate; and

a first electrode in the third insulating layer and a second electrode in the fourth insulating layer that are bonded to each other, wherein the first electrode and the second electrode are disposed in a peripheral region, and wherein the peripheral region does not overlap the plurality of pixels.

2 . The light detecting device according to claim 1 , wherein the first via is in the peripheral region.

3 . The light detecting device according to claim 2 , further comprising a second via that passes through the second semiconductor substrate, wherein the second electrode overlaps with at least a part of the plurality of pixels in a plan view.

4 . The light detecting device according to claim 3 , further comprising a third electrode in the third insulating layer and a fourth electrode in the fourth insulating layer, wherein the third electrode and the fourth electrode are bonded to each other.

5 . The light detecting device according to claim 4 , wherein the third electrode and the fourth electrode overlap with a part of the plurality of pixels.

6 . The light detecting device according to claim 5 , further comprising:

a fifth electrode in the first insulating layer; and

a sixth electrode in the second insulating layer, wherein the fifth electrode and the sixth electrode are bonded to each other.

7 . The light detecting device according to claim 2 , wherein the first via extends between the second insulating layer and the third insulating layer.

8 . The light detecting device according to claim 7 , wherein the first via is bonded to a third electrode in the second insulating layer and to the first electrode in the third insulating layer.

9 . The light detecting device according to claim 8 , wherein a fourth electrode in the first insulating layer is bonded to a fifth electrode in the second insulating layer.

10 . The light detecting device according to claim 1 , wherein the plurality of pixels are disposed in a two-dimensional array.

11 . The light detecting device according to claim 1 , wherein the first insulating layer is part of a first multi-layered wiring layer, and wherein the second insulating layer is part of a second multi-layered wiring layer.

12 . The light detecting device according to claim 11 , wherein the third insulating layer is part of a third multi-layered wiring layer, and wherein the fourth insulating layer is part of a fourth multi-layered wiring layer.

13 . An electronic apparatus, comprising:

an imaging device, including:

a first structure including a first semiconductor substrate and a first insulating layer, the first semiconductor substrate having a plurality of pixels;

a second structure including a second semiconductor substrate, a second insulating layer, and a third insulating layer; and

a third structure including a third semiconductor substrate and a fourth insulating layer,

wherein the first structure and the second structure are bonded together such that the first insulating layer and the second insulating layer are adjacent to each other, and

wherein the second structure and the third structure are bonded together such that the third insulating layer and the fourth insulating layer are adjacent to each other;

a first via that passes through the second semiconductor substrate; and

a first electrode in the third insulating layer and a second electrode in the fourth insulating layer that are bonded to each other, wherein the first electrode and the second electrode are disposed in a peripheral region, and wherein the peripheral region does not overlap the plurality of pixels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2024
From: KAMESHIMA, TAKATOSHI; MITSUHASHI, IKUE; HASHIGUCHI, HIDETO; IIJIMA, TADASHI; SHOHJI, REIJIROH; HANEDA, MASAKI; HORIKOSHI, HIROSHI; ISHIDA, MINORU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 066647/0118 →
Priority Claims (2)
JP 2017-074807 · Apr 4, 2017 · national
JP 2017-130384 · Jul 3, 2017 · national
Continuity (3)
Continuation 17592025 · Feb 3, 2022
Continuation 16497084
Related Publication 20240274641A1 · Aug 15, 2024
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