IP Library › Granted Patent US 12,666,974
Granted Patent B2
US 12,666,974 · App. 18/142,357 · Granted Jun 23, 2026

Silver sintered molybdenum (SSM) packaging for power semiconductor devices

Inventors: Yuhang Yang (Hamilton, CA); Ali Emadi (Burlington, CA)
Assignee: McMaster University
H10W70/417H10W40/258H10W70/04H10W72/07331H10W72/07631H10W72/352H10W72/886H10W72/952H10W90/736H10W90/766
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,666,974
App. No.
18/142,357
Filed
May 2, 2023
Granted
Jun 23, 2026
Kind
B2
Art Unit
2898
USPC
257/676
Abstract

The present disclosure generally relates to a silver sintered molybdenum (SSM) packaging for power semiconductor devices and a method of manufacturing thereof. The SSM packaging comprises a substrate; a MOSFET die comprising a first side and a second side, wherein the first side is bonded to the substrate using nano silver sintering; and at least two leads connected, at a respective first end, to the substrate and, at a respective second end, to the second side of the MOSFET die, wherein nano silver sintering is used to bond the first and second ends of the at least two leads, and wherein each of the substrate and at least two leads is formed of pure molybdenum.

Claims (10)

1 . A packaging module comprising:

a substrate;

a MOSFET die comprising a first side and a second side, wherein the first side is bonded to the substrate using nano silver sintering; and

at least two leads connected, at a respective first end, to the substrate and, at a respective second end, to the second side of the MOSFET die, wherein nano silver sintering is used to bond the first and second ends of the at least two leads, and

wherein each of the substrate and the at least two leads is formed of pure molybdenum.

2 . The packaging module of claim 1 , wherein the MOSFET die comprises a silicon carbide (SiC) die.

3 . The packaging module of claim 1 , further comprising a heat sink stacked below the substrate, and the heat sink is also formed of pure molybdenum.

4 . The packaging module of claim 3 , further comprising an insulator layer stacked between the heat sink and the substrate.

5 . The packaging module of claim 4 , wherein the insulator layer is formed of bismaleimide triazine resin.

6 . The packaging of claim 1 , wherein the substrate includes a first substrate side and a second substrate side, and the first substrate side is coated with ruthenium (Ru)/silver (Ag).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2023
From: EMADI, ALI; YANG, YUHANG
To: MCMASTER UNIVERSITY
Reel/Frame 063862/0809 →
Continuity (2)
Provisional Application 63337357 · May 2, 2022
Related Publication 20230352372A1 · Nov 2, 2023
References Cited (28)
US 6396125B1 · Soyano · 2002 [cited by applicant]
US 7842545B2 · Lee · 2010 [cited by applicant]
US 9123639B2 · Kimijima et al. · 2015 [cited by applicant]
US 9551082B2 · Shashkov et al. · 2017 [cited by applicant]
US 10212838B2 · McPherson et al. · 2019 [cited by applicant]
US 20070257351A1 · Lee et al. · 2007 [cited by applicant]
US 20120286292A1 · Nakayama et al. · 2012 [cited by applicant]
US 20140312360A1 · Otremba · 2014 [cited by examiner]
US 20140353808A1 · Hosseini · 2014 [cited by examiner]
US 20150077941A1 · Hosseini · 2015 [cited by examiner]
US 20150115452A1 · Yoon · 2015 [cited by examiner]
US 20160358838A1 · Basler · 2016 [cited by examiner]
US 20220108975A1 · Manola · 2022 [cited by examiner]
US 20220130773A1 · Pun · 2022 [cited by examiner]
US 20230215833A1 · Namishia · 2023 [cited by examiner]
CN 207165543U · 2018 [cited by examiner]
CN 111477683A · 2020 [cited by applicant]
JP 2021114537A · 2021 [cited by examiner]
WO WO2015086184A1 · 2015 [cited by examiner]
WO WO2016125419A1 · 2016 [cited by examiner]
WO 2019071742A1 · 2019 [cited by applicant]
“Reliability Assessment of Sintered Nano-Silver Die Attachment for Power Semiconductors”, Matthias Knoerr et al., Fraunhofer Institute for Integrated Systems and Device Technology, May 2, 2022, p. 56-61. [cited by applicant]
“High Temperature LTCC based SiC Double-Sided Cooling Power Electronic Module”, Hao Zhang, University of Arkansas, Fayetteville, May 2014. [cited by applicant]
“Die Attach of Power Devices Using Silver Sintering-Bonding Process Optimization and Characterization”, Cyril Buttay et al., HiTEN 2011, Jul. 2011, Oxford, United Kingdom, pp. 1-7, hal-00672619. [cited by applicant]
“Applying Anand model to low-temperature sintered nanoscale silver paste chip attachment”, Dun-ji Yu, et al., Materials and Design 30 (2009), 4574-4579. [cited by applicant]
“Tensile Behaviors and Ratcheting Effects of Partially Sintered Chip-Attachment Films of a Nanoscale Silver Paste”, Xu Chen et al., Journal of Electronic Materials, vol. 37, No. 10, 2008, pp. 1574-1579. [cited by applicant]
“Modeling and Analysis of Silver-Sintered Molybdenum Packaging for SiC Power Modules With Improved Lifetime and Temperature Range”, Yuhang Yang et al., IEEE Transactions on Components, Packaging and Manufacturing Techno… [cited by applicant]
“Thermal-Electrical Modeling and Co-Optimization of a Half-Bridge Power Module with Silver-Sintered Molybdenum Packaging”, Yuhang Yang et al., IEEE Transactions on Power Electronics, pp. 1-12, published May 30, 2023. [cited by applicant]