IP Library Granted Patent US 12,671,949
Granted Patent B2
US 12,671,949 · App. 18/374,739 · Granted Jun 30, 2026

Synchronized audio streaming from multiple controllers

Inventors: Carl Kittredge Wakeland (Santa Clara, CA); Uma Sankara Rao Balla (Hyderabad, IN)
Assignee: ADVANCED MICRO DEVICES, INC.
H04S3/008G06F3/162H04S2400/01
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Quick Facts
Patent No.
US 12,671,949
App. No.
18/374,739
Filed
Sep 29, 2023
Granted
Jun 30, 2026
Kind
B2
Art Unit
2695
USPC
381/1
Abstract

A processing system includes a hardware synchronizer to synchronize the transmission of audio data from multiple I2S controllers of a processing system to one or more audio codecs. In some embodiments, each of the I2S controllers receives audio data from one or more audio data sources and stores the audio data at a buffer associated with the controller. The hardware synchronizer initiates synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level. In some embodiments, until the controllers begin transmission of the audio data, the controllers transmit mute (null) data to the one or more codecs such that the one or more codecs receives a frame start followed by null data for each frame.

Claims (31)

1 . A method comprising:

receiving audio data at a plurality of controllers of an audio system;

storing the audio data at a plurality of buffers, each buffer of the plurality of buffers associated with a controller of the plurality of controllers; and

initiating synchronized transmission of the audio data from each controller to one or more codecs in response to the plurality of buffers being filled to a predetermined level.

2 . The method of claim 1 , further comprising:

fetching the audio data to each controller of the plurality of controllers using a direct memory access engine associated with each controller.

3 . The method of claim 2 , wherein fetching the audio data to each of controller of the plurality of controllers is performed asynchronously.

4 . The method of claim 1 , further comprising:

sending a signal from each controller that the buffer associated with the controller is filled to the predetermined level.

5 . The method of claim 4 , wherein initiating synchronized transmission is further in response to receiving the signal from each controller of the plurality of controllers.

6 . The method of claim 1 , wherein the plurality of controllers is a subset of controllers of the audio system.

7 . The method of claim 1 , further comprising:

transmitting null data from each controller to the one or more codecs prior to initiating synchronized transmission of the audio data.

8 . An audio system, comprising:

a plurality of controllers, each controller configured to receive audio data and store the audio data at a buffer associated with the controller;

one or more codecs configured to receive the audio data from the plurality of controllers; and

a hardware synchronizer configured to initiate synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level.

9 . The audio system of claim 8 , wherein each controller of the plurality of controllers is associated with a direct memory access (DMA) engine configured to fetch the audio data to each controller.

10 . The audio system of claim 9 , wherein each DMA engine is configured to fetch the audio data asynchronously from the other DMA engines.

11 . The audio system of claim 8 , wherein each controller is configured to send a signal to the hardware synchronizer indicating that the buffer associated with the controller is filled to the predetermined level.

12 . The audio system of claim 11 , wherein the hardware synchronizer is further configured to initiate synchronized transmission in response to receiving the signal from each controller of the plurality of controllers.

13 . The audio system of claim 8 , wherein the plurality of controllers is a subset of controllers of the audio system.

14 . The audio system of claim 8 , wherein each of the plurality of controllers is further configured to transmit null data to the one or more codecs prior to the synchronized transmission of the audio data.

15 . A system, comprising:

a plurality of buffers, each buffer associated with a controller of a plurality of controllers and configured to receive audio data; and

a hardware synchronizer configured to initiate synchronized transmission of the audio data from at least a subset of the plurality of controllers to one or more codecs in response to the plurality of buffers being filled to a predetermined level.

16 . The system of claim 15 , wherein each controller of the plurality of controllers is associated with a direct memory access (DMA) engine configured to fetch the audio data to each controller.

17 . The system of claim 16 , wherein each DMA engine is configured to fetch the audio data asynchronously from the other DMA engines.

18 . The system of claim 15 , wherein each controller is configured to send a signal to the hardware synchronizer indicating that the buffer associated with the controller is filled to the predetermined level.

19 . The system of claim 18 , wherein the hardware synchronizer is further configured to initiate synchronized transmission in response to receiving the signal from each controller of the plurality of controllers.

20 . The system of claim 15 , wherein each of the plurality of controllers is further configured to transmit null data to the one or more codecs prior to the synchronized transmission of the audio data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2023
From: WAKELAND, CARL KITTREDGE; BALLA, UMA SANKARA RAO
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 065471/0639 →
Continuity (1)
Related Publication 20250113153A1 · Apr 3, 2025
References Cited (69)
US 5202991A · Gamache · 1993 [cited by applicant]
US 5321825A · Song · 1994 [cited by applicant]
US 5390324A · Burckhartt et al. · 1995 [cited by applicant]
US 5611042A · Lordi · 1997 [cited by applicant]
US 5729472A · Seiffert et al. · 1998 [cited by applicant]
US 5987628A · Von Bokern et al. · 1999 [cited by applicant]
US 6370656B1 · Olarig et al. · 2002 [cited by applicant]
US 6446145B1 · Har et al. · 2002 [cited by applicant]
US 6584587B1 · McDermott · 2003 [cited by applicant]
US 6640268B1 · Kumar · 2003 [cited by applicant]
US 7426644B1 · Strongin et al. · 2008 [cited by applicant]
US 7477073B1 · Tuan et al. · 2009 [cited by applicant]
US 8824692B2 · Sheerin et al. · 2014 [cited by applicant]
US 9122476B2 · Serebrin et al. · 2015 [cited by applicant]
US 9411688B1 · Poolla et al. · 2016 [cited by applicant]
US 10153046B1 · Agarwal et al. · 2018 [cited by applicant]
US 10209952B2 · Tanaka · 2019 [cited by examiner]
US 10585899B2 · Usami et al. · 2020 [cited by applicant]
US 10749488B2 · Quilter et al. · 2020 [cited by applicant]
US 11496577B2 · Acharya et al. · 2022 [cited by applicant]
US 11558706B2 · Lesso · 2023 [cited by applicant]
US 11960436B2 · Ben-Amram · 2024 [cited by examiner]
US 20030115564A1 · Chang et al. · 2003 [cited by applicant]
US 20080140957A1 · Pattabiraman et al. · 2008 [cited by applicant]
US 20080147918A1 · Hanebutte · 2008 [cited by examiner]
US 20080195902A1 · Astigarraga et al. · 2008 [cited by applicant]
US 20080320366A1 · Lin · 2008 [cited by applicant]
US 20090282393A1 · Costa et al. · 2009 [cited by applicant]
US 20100125427A1 · Gaiser et al. · 2010 [cited by applicant]
US 20100125444A1 · Arya et al. · 2010 [cited by applicant]
US 20120054543A1 · Dreier · 2012 [cited by applicant]
US 20130254586A1 · Winger et al. · 2013 [cited by applicant]
US 20140095947A1 · Mozak et al. · 2014 [cited by applicant]
US 20150019154A1 · Usami et al. · 2015 [cited by applicant]
US 20150055406A1 · Andre · 2015 [cited by applicant]
US 20160364343A1 · Case et al. · 2016 [cited by applicant]
US 20190278733A1 · Kessler · 2019 [cited by examiner]
US 20210182132A1 · Chen et al. · 2021 [cited by applicant]
US 20220013127A1 · Goldstein et al. · 2022 [cited by applicant]
US 20220013149A1 · Rentschler · 2022 [cited by examiner]
US 20220121474A1 · Brewer · 2022 [cited by applicant]
US 20230053582A1 · Muralidharan et al. · 2023 [cited by applicant]
US 20230304266A1 · Suzuki et al. · 2023 [cited by applicant]
US 20230350842A1 · Ben-Amram · 2023 [cited by examiner]
US 20230370184A1 · Robertson · 2023 [cited by examiner]
US 20240281325A1 · Arbel et al. · 2024 [cited by applicant]
US 20240406693A1 · Veloso et al. · 2024 [cited by applicant]
US 20250091436A1 · Enapakurthi et al. · 2025 [cited by applicant]
CN 111683855 · 2020 [cited by applicant]
KR 1020040010957 · 2004 [cited by applicant]
KR 10201900955338 · 2019 [cited by applicant]
WO 2022252063 · 2022 [cited by applicant]
U.S. Appl. No. 18/539,629, filed Dec. 14, 2023, listing Carl Kittredge Wakeland et al. as inventors, Entitled “Hardware Audio Modification System”, 25 pages. [cited by applicant]
U.S. Appl. No. 18/617,112, filed Mar. 26, 2024, listing Uma Sankara Rao Balla et al. as inventors, Entitled “Shared Memory Freedom From Interference System”, 49 pages. [cited by applicant]
U.S. Appl. No. 18/389,056, filed Nov. 13, 2023, listing Uma Sankara Rao Balla et al. as inventors, Entitled “Error Detection for Sram Used in a Safety-Critical Domain”, 49 pages. [cited by applicant]
U.S. Appl. No. 18/375,294, filed Sep. 29, 2023, listing Andy Sung et al. as inventors, Entitled “Boot Ram for Safety Critical Domain”, 24 pages. [cited by applicant]
U.S. Appl. No. 18/398,411, filed Dec. 28, 2023, listing Balatripura S. Chavali et al. as inventors, Entitled “Transactional Timeouts for Managing Critical Domains”, 32 pages. [cited by applicant]
Non-Final Office Action mailed Dec. 18, 2024 for U.S. Appl. No. 18/389,056, 21 pages. [cited by applicant]
Non-Final Office Action mailed Mar. 13, 2025 for U.S. Appl. No. 18/375,294, 38 pages. [cited by applicant]
Final Office Action mailed Mar. 28, 2025 for U.S. Appl. No. 18/389,056, 42 pages. [cited by applicant]
Non-Final Office Action mailed May 30, 2025 for U.S. Appl. No. 18/398,411, 11 pages. [cited by applicant]
Non-Final Office Action mailed Jul. 3, 2025 for U.S. Appl. No. 18/389,056, 20 pages. [cited by applicant]
International Search Report and Written Opinion mailed Jun. 23, 2025 for PCT/US2025/019780, 10 pages. [cited by applicant]
International Search Report and Written Opinion issued in Application No. PCT/US/2024/034054, mailed Oct. 8, 2024, 10 pages. [cited by applicant]
Non-Final Office Action mailed Oct. 28, 2025 for U.S. Appl. No. 18/539,629, 13 pages. [cited by applicant]
Non-Final Office Action mailed Sep. 30, 2025 for U.S. Appl. No. 18/617,112, 13 pages. [cited by applicant]
Final Office Action mailed Oct. 24, 2025 for U.S. Appl. No. 18/389,056, 22 pages. [cited by applicant]
Non-Final Office Action mailed Sep. 24, 2025 for U.S. Appl. No. 18/375,294, 8 pages. [cited by applicant]
Non-Final Office Action mailed Oct. 2, 2025 for U.S. Appl. No. 18/398,411, 11 pages. [cited by applicant]