Granted Patent B2

US 12,672,357 · App. 17/499,970 · Granted Jun 30, 2026

Inventors: Oreste Madia (Leuven, BE); Giuseppe Alessio Verni (Jodoigne, BE); Qi Xie (Wilsele, BE); Michael Eugene Givens (Oud-Heverlee, BE); Varun Sharma (Helsinki, FI); Andrea Illiberi (Leuven, BE)

Assignee: ASM IP Holding B.V.

H10D99/00H10P14/6339

Abstract

Claims (29)

1 . A method for depositing a layer for controlling a threshold voltage of a metal-oxide-semiconductor field effect transistor (MOSFET), the method comprising the steps of:

providing a substrate within a reactor chamber, the substrate comprising a source region, a drain region, a channel region, a silicon oxide interfacial layer formed over the channel region, and a surface, the surface comprising a silicon oxide surface or a high k dielectric surface formed over the silicon oxide interfacial layer;

depositing a threshold voltage shifting layer comprising gallium oxide directly onto the silicon oxide surface or on the high k dielectric surface using a cyclical deposition process, wherein depositing the threshold voltage shifting layer comprising gallium oxide comprises;

in sequence:

providing a gallium precursor to the reaction chamber for a first pulse;

providing a first oxygen reactant comprising ozone to the reaction chamber;

providing the gallium precursor to the reaction chamber for a second pulse; and

providing a second oxygen reactant comprising water to the reaction chamber, and

wherein the first oxygen reactant is different from the second oxygen reactant.

2 . The method according to claim 1 wherein the gallium precursor is selected from the list: gallium beta diketonates, gallium alkoxides, and gallanes.

3 . The method according to claim 1 , wherein the gallium precursor is selected from the list consisting of dimethylgallium isopropoxide.

4 . The method according to claim 1 wherein the threshold voltage shifting layer further comprises indium, and wherein the cyclic deposition process further comprises a step of providing an indium precursor to the reaction chamber.

5 . The method according to claim 4 wherein the cyclic deposition process comprises a plurality of pulses, the plurality of pulses comprises one or more gallium precursor pulses, one or more indium precursor pulses, and one or more oxygen reactant pulses; wherein the gallium precursor is provided to the reaction chamber in the one or more gallium precursor pulses, wherein the indium precursor is provided to the reaction chamber in the indium precursor pulse, wherein the oxygen reactant is provided to the reaction chamber in oxygen reactant pulses; and wherein the pulses are provided in any one of the following sequences:

gallium precursor pulse, indium precursor pulse, oxygen reactant pulse; or,

indium precursor pulse, gallium precursor pulse, oxygen reactant pulse.

6 . The method according to claim 4 , wherein the indium precursor is selected from indium beta diketonates, indium alkoxides, and indium alkylamides.

7 . The method according to claim 1 wherein the threshold voltage shifting layer further comprises zinc, and wherein the cyclic deposition process further comprises a step of providing a zinc precursor to the reaction chamber.

8 . The method according to claim 7 wherein the zinc precursor is selected from zinc beta diketonates, zinc alkoxides, and zinc alkylamides.

9 . The method according to claim 1 wherein the threshold voltage shifting layer further comprises tin, and wherein the cyclic deposition process further comprises a step of providing a tin precursor to the reaction chamber.

10 . The method according to claim 9 wherein the tin precursor is selected from tin alkyls, tin halides, tin beta diketonates, tin alkoxides, and tin alkylamides.

11 . The method according to claim 1 wherein the threshold voltage shifting layer has a thickness from at least 0.03 nm to at most 1.0 nm.

12 . The method according to claim 1 wherein the threshold voltage shifting layer is deposited at a temperature of at least 80° C. to at most 300° C.

13 . The method according to claim 1 wherein the threshold voltage shifting layer is deposited at a pressure of at least 1.0 Torr to at most 10.0 Torr.

14 . The method according to claim 1 , wherein the cyclical deposition process comprises a cyclical chemical vapor deposition process.

15 . The method according to claim 1 , wherein the cyclical deposition process is a thermal process.

16 . A structure comprising the threshold voltage shifting layer formed according to a method according to claim 1 .

17 . The structure according to claim 16 , comprising the high-k dielectric layer between the threshold voltage shifting layer and the silicon oxide interfacial layer.

18 . The structure according to claim 16 , wherein the threshold voltage shifting layer is positioned between the high-k dielectric layer and the silicon oxide interfacial layer.

19 . The method of claim 1 , wherein the first oxygen reactant consists of ozone and the second oxygen reactant consists of water.

Assignments (1)

Continuity (2)

References Cited (400)