Granted Patent B2

US 12,681,862 · App. 18/772,045 · Granted Jul 14, 2026

Inventors: Michael Wasef (San Jose, CA); Andrew Chang (Los Altos, CA)

Assignee: Samsung Electronics Co., Ltd.

G06F12/0862G06F3/0604G06F3/0655G06F3/0679G06F2212/602

Abstract

Claims (53)

1 . A storage device comprising:

a first storage medium associated with a first access latency;

a second storage medium associated with a second access latency lower than the first access latency;

a processor configured to:

identify, based on a request from an application, a first physical memory address of the first storage medium;

identify, based on the request, a first range of physical memory addresses of a first region of the first storage medium based on the first physical memory address;

identify a second range of physical memory addresses of a portion of the first region based on the first physical memory address;

identify a number of memory accesses associated with the portion; and

access the first storage medium over a data interface connection and retrieve data associated with the portion from the first storage medium to the second storage medium based on the number of memory accesses to the portion.

2 . The storage device of claim 1 , wherein the processor being configured to identify the second range of physical memory addresses is based on the first physical memory address being a threshold distance away from a second memory address.

3 . The storage device of claim 1 , wherein the processor is configured to:

identify a second memory address of the second range of physical memory addresses satisfying a third criterion;

identify a third memory address of the second range of physical memory addresses satisfying a fourth criterion; and

retrieve data between the second memory address and the third memory address.

4 . The storage device of claim 1 , wherein the processor is further configured to:

update a counter associated with the portion based on access of the first physical memory address.

5 . The storage device of claim 4 , wherein the processor being configured to identify the number of memory accesses associated with the portion is based on the counter being greater than a threshold value.

6 . The storage device of claim 1 , wherein the processor is further configured to:

maintain a list of identified portions;

determine a number of the identified portions in the list;

determine that the number of the identified portions is less than a threshold number; and

add the portion to the list based on the number of the identified portions being less than the threshold number.

7 . The storage device of claim 6 , wherein the processor being configured to retrieve the data is based on the portion being added to the list.

8 . The storage device of claim 6 , wherein the processor is further configured to:

detect a condition;

based on detecting the condition, identify a third criterion associated with the portion; and

based on identifying the third criterion, remove the portion from the list.

9 . The storage device of claim 8 , wherein the third criterion is based on an access of an address associated with the portion.

10 . A method comprising:

identifying, based on a request from an application, a first physical memory address of a first storage medium;

identifying, based on the request, a first range of physical memory addresses of a first region of a first storage medium based on the first physical memory address;

identifying a second range of physical memory addresses of a portion of the first region based on the first physical memory address;

identifying a number of memory accesses associated with the portion; and

accessing the first storage medium over a data interface connection and retrieving data associated with the portion from the first storage medium to a second storage medium based on the number of memory accesses to the portion, wherein the first storage medium is associated with a first access latency and the second storage medium is associated with a second access latency lower than the first access latency.

11 . The method of claim 10 , wherein the identifying of the second range of physical memory addresses is based on the first physical memory address being a threshold distance away from a second memory address.

12 . The method of claim 10 further comprising:

identifying a second memory address of the second range of physical memory addresses satisfying a third criterion;

identifying a third memory address of the second range of physical memory addresses satisfying a fourth criterion; and

retrieving data between the second memory address and the third memory address.

13 . The method of claim 10 further comprising:

updating a counter associated with the portion based on access of the first physical memory address.

14 . The method of claim 13 , wherein the identifying of the number of memory accesses associated with the portion is based on the counter being greater than a threshold value.

15 . The method of claim 10 further comprising:

maintaining a list of identified portions;

determining a number of the identified portions in the list;

determining that the number of the identified portions is less than a threshold number; and

adding the portion to the list based on the number of the identified portions being less than the threshold number.

16 . The method of claim 15 further comprising retrieving the data based on the portion being added to the list.

17 . The method of claim 15 further comprising:

detecting a condition;

based on detecting the condition, identifying a third criterion associated with the portion; and

based on identifying the third criterion, removing the portion from the list.

18 . The method of claim 17 , wherein the third criterion is based on an access of an address associated with the portion.

Assignments (1)

Continuity (2)

References Cited (54)