IP Library › Granted Patent US 12,683,708
Granted Patent B2
US 12,683,708 · App. 18/168,564 · Granted Jul 14, 2026

Waveform control method, radio device, and integrated circuit

Inventors: Fazhi An (Shanghai, CN); Yafei Shi (Shanghai, CN); Tao Gong (Shanghai, CN)
Assignee: Calterah Semiconductor Technology (Shanghai) Co., Ltd.
H04L1/0006H04L27/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,683,708
App. No.
18/168,564
Filed
Feb 13, 2023
Granted
Jul 14, 2026
Kind
B2
Examiner
TRAN, PHUC H
Art Unit
2471
USPC
370/328
Abstract

Embodiments of the present disclosure provide a waveform control method, a radio device, a radio signal, a signal transmission link and an integrated circuit. The waveform control method includes: calling, by a chip structure, at least two types of frame-configuration parameters from an external storage and storing the frame-configuration parameters in a memory; acquiring a frame order, and calling corresponding frame-configuration parameters from the memory in sequence according to the frame order; and generating frame period signals according to the corresponding frame-configuration parameters. The frame period signals include at least two frames of signals.

Claims (34)

1 . A waveform control method for controlling a waveform of a signal transmitted by a radio device, wherein the radio device comprises a chip structure having a memory and further comprises or has access to an external storage, and the method comprises:

reading frame-configuration parameters from the external storage and storing the frame-configuration parameters in the memory, wherein the frame-configuration parameters are of a plurality of types, and frame-configuration parameters of a respective type correspond to a respective waveform of a signal transmitted in a respective frame;

reading corresponding frame-configuration parameters from the memory in sequence according to a configurable frame-configuration parameter order; and

generating frame period signals according to the corresponding frame-configuration parameters;

wherein the frame period signals comprise a plurality of frames of signals, and at least two of the plurality of frames respectively correspond to at least two types of the plurality of types.

2 . The waveform control method according to claim 1 , wherein the corresponding frame-configuration parameters include a first frame configuration parameter corresponding to a first frame of at least two adjacent frames in the frame period signals and a second frame configuration parameter corresponding to a second frame of the at least two adjacent frames, and wherein the first frame configuration parameter and the second frame configuration parameter are different.

3 . The waveform control method according to claim 1 , wherein reading the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order comprises:

periodically and circularly reading the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order.

4 . The waveform control method according to claim 1 , wherein reading the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order comprises:

acquiring application environment parameters; and

selecting a corresponding configurable frame-configuration parameter order according to intervals in which the application environment parameters fall.

5 . The waveform control method according to claim 1 , wherein before reading the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order, the waveform control method comprises:

acquiring a set of random numbers; and

generating a corresponding configurable frame-configuration parameter order according to the set of random numbers.

6 . A radio device, comprising a chip structure and an external storage, wherein frame-configuration parameters are pre-stored in the external storage, and wherein the chip structure comprises:

a memory, configured to store the frame-configuration parameters before frame period signals are transmitted, wherein the frame-configuration parameters are of a plurality of types;

a frame period control logic circuit, configured to output a configurable frame-configuration parameter order;

a frame configuration automatic acquisition logic circuit, connected to the memory and the frame period control logic circuit and configured to read corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order; and

a radio wave generation logic circuit, connected to the frame configuration automatic acquisition logic circuit and configured to generate the frame period signals according to the corresponding frame-configuration parameters;

wherein the frame period signals comprise a plurality of frames of signals, at least two of the plurality of frames respectively corresponding to at least two types of the plurality of types, and wherein frame-configuration parameters of a respective type correspond to a respective waveform of a signal transmitted in a respective frame.

7 . The radio device according to claim 6 , wherein the corresponding frame-configuration parameters include a first frame configuration parameter corresponding to a first frame of at least two adjacent frames in the frame period signals and a second frame configuration parameter corresponding to a second frame of the at least two adjacent frames, and wherein the first frame configuration parameter and the second frame configuration parameter are different.

8 . The radio device according to claim 6 , wherein the frame configuration automatic acquisition logic circuit is further configured to periodically and circularly read the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order.

9 . The radio device according to claim 6 , wherein the frame period control logic circuit is further configured to acquire application environment parameters and to output corresponding configurable frame-configuration parameter order according to intervals in which the application environment parameters fall.

10 . The radio device according to claim 6 , wherein the frame period control logic circuit is further configured to acquire a set of random numbers and generate corresponding configurable frame-configuration parameter order according to the set of random numbers.

11 . An integrated circuit, operable in a radio device comprising an external storage in which frame-configuration parameters are pre-stored, wherein the integrated circuit comprising:

a memory, configured to store the frame-configuration parameters before frame period signals being transmitted, wherein the frame-configuration parameters are of a plurality of types;

a frame period control logic circuit, configured to output a configurable frame-configuration parameter order;

a frame configuration automatic acquisition logic circuit, connected to the memory and the frame period control logic circuit and configured to read corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order; and

a radio wave generation logic circuit, connected to the frame configuration automatic acquisition logic circuit, and configured to generate the frame period signals according to the corresponding frame-configuration parameters;

wherein the frame period signals comprise a plurality of frames of signals, at least two of the plurality of frames respectively corresponding to at least two types of the plurality of types, and wherein frame-configuration parameters of a respective type correspond to a respective waveform of a signal transmitted in a respective frame.

12 . The integrated circuit according to claim 11 , wherein the corresponding frame-configuration parameters include a first frame configuration parameter corresponding to a first frame of at least two adjacent frames in the frame period signals and a second frame configuration parameter corresponding to a second frame of the at least two adjacent frames, and wherein the first frame configuration parameter and the second frame configuration parameter are different.

13 . The integrated circuit according to claim 11 , wherein the frame configuration automatic acquisition logic circuit is further configured to periodically and circularly read the corresponding frame-configuration parameters from the memory in sequence according to the configurable frame-configuration parameter order.

14 . The integrated circuit according to claim 11 , wherein the frame period control logic circuit is further configured to acquire application environment parameters and to output corresponding configurable frame-configuration parameter order according to intervals in which the application environment parameters fall.

15 . The integrated circuit according to claim 11 , wherein the frame period control logic circuit is further configured to acquire a set of random numbers and generate corresponding configurable frame-configuration parameter order according to the set of random numbers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2025
From: AN, FAZHI; SHI, YAFEI; GONG, TAO
To: CALTERAH SEMICONDUCTOR TECHNOLOGY (SHANGHAI) CO., LTD.
Reel/Frame 071069/0536 →
Priority Claims (1)
CN 202111165913.5 · Sep 30, 2021 · national
Continuity (2)
Continuation PCTCN2022111563 · Aug 10, 2022
Related Publication 20230198657A1 · Jun 22, 2023
References Cited (34)
US 5050161A · Golestani · 1991 [cited by examiner]
US 12114297B2 · Liu · 2024 [cited by examiner]
US 20090144596A1 · Mohan · 2009 [cited by examiner]
US 20090296854A1 · Yamano · 2009 [cited by examiner]
US 20100054329A1 · Bronstein · 2010 [cited by examiner]
US 20150043467A1 · Kondo et al. · 2015 [cited by applicant]
US 20150071153A1 · Hong · 2015 [cited by examiner]
US 20160204887A1 · Lee · 2016 [cited by examiner]
US 20160327633A1 · Kumar Y.B. · 2016 [cited by examiner]
US 20170315659A1 · Kuroiwa et al. · 2017 [cited by applicant]
US 20180123754A1 · Kim et al. · 2018 [cited by applicant]
US 20180301816A1 · Kamo et al. · 2018 [cited by applicant]
US 20200025870A1 · Melzer et al. · 2020 [cited by applicant]
US 20200322977A1 · Yasukawa et al. · 2020 [cited by applicant]
CN 101447826A · 2009 [cited by applicant]
CN 105900527A · 2016 [cited by applicant]
CN 107710011A · 2018 [cited by applicant]
CN 107766764A · 2018 [cited by applicant]
CN 109085543A · 2018 [cited by applicant]
CN 111600680A · 2020 [cited by applicant]
CN 111693996A · 2020 [cited by applicant]
CN 111983597A · 2020 [cited by applicant]
CN 112437206A · 2021 [cited by applicant]
CN 112764036A · 2021 [cited by applicant]
CN 113325374A · 2021 [cited by applicant]
EP 3860264A1 · 2021 [cited by applicant]
WO 2021031077A1 · 2021 [cited by applicant]
Calterah Semiconductor Technology (shanghai) Co., Ltd., The Second Office Action with English translation, CN 2021111659135, Apr. 29, 2024, 9 pgs. [cited by applicant]
Guanyuan Chen, et al., “Design of variable-frequency AWG”, Science Technology and Engineering, vol. 17 No. 3, Jan. 28, 2017, 4 pgs. [cited by applicant]
Zhenghui Chen, et al., “Design for MIMO Radar and Implementation of OFDM-LFM Waveform”, Radar Science and Technology, vol. 11 No. 1,Feb. 15, 2013, 5 pgs. [cited by applicant]
Zhiyi Duan, et al., “A novel FMCW waveform for multi-target detection and the corresponding algorithm”, 2017 IEEE 5th International Symposium on Electromagnetic Compatibility (EMC-Beijing), Jan. 18, 2018, 4 pgs. [cited by applicant]
Calterah Semiconductor Technology (shanghai) Co., Ltd., International Search Report with English translation, PCT/CN2022/111563, Nov. 2, 2022, 6 pgs. [cited by applicant]
Calterah Semiconductor Technology (Shanghai) Co., Ltd., European Search Report, EP22806881.3, Jan. 14, 2025, 7 pgs. [cited by applicant]
Calterah Semiconductor Technology (Shanghai) Co., Ltd., European Communication pursuant to Article 94(3) EPC, EP22806881.3, Sep. 29, 2025, 8 pgs. [cited by applicant]